JPS5942657U - Reception frequency display device - Google Patents
Reception frequency display deviceInfo
- Publication number
- JPS5942657U JPS5942657U JP6967683U JP6967683U JPS5942657U JP S5942657 U JPS5942657 U JP S5942657U JP 6967683 U JP6967683 U JP 6967683U JP 6967683 U JP6967683 U JP 6967683U JP S5942657 U JPS5942657 U JP S5942657U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- display device
- cascade
- mixer
- bfo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Measuring Frequencies, Analyzing Spectra (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は、本考案の一実施例を示す受信周波数表示装置のブ
ロック図である。
１・・・局部発振器、２，４・・・カウンタ、３・・・
ＢＦＯ１５・・・演算回路、６・・・表示器。The figure is a block diagram of a received frequency display device showing an embodiment of the present invention. 1... Local oscillator, 2, 4... Counter, 3...
BFO15...Arithmetic circuit, 6...Display device.
Claims (1)
スーパーヘテロゲイン式受信回路において、第１のミク
サへは局部発振器とカウンタとを縦続結線し、第２のミ
クサへはＢＦＯと他のカウンタとを縦続結線して、夫々
のカウンタの出力側をデジタル演算回路へ結線すると共
に該デジタル演算回路と表示器とを結線し、局部発振周
波数とＢＦＯ周波数とを夫々別個に設けたカウンタで計
測してそのデジタル出力を演算して表示し、ＢＦＯ周波
数の存在しないときには中間周波数の中心周波数に等し
いデジタル値を演算回路に与えて表示することを特徴と
する受信周波数表示装置。In a superhetero gain receiving circuit in which a first mixer, an amplifier, and a second mixer are connected in cascade, a local oscillator and a counter are connected in cascade to the first mixer, and a BFO and other The counters are connected in cascade, the output side of each counter is connected to a digital arithmetic circuit, and the digital arithmetic circuit and the display are connected, and the local oscillation frequency and BFO frequency are measured with separate counters. A reception frequency display device characterized in that the digital output is calculated and displayed, and when a BFO frequency does not exist, a digital value equal to the center frequency of the intermediate frequency is given to the calculation circuit and displayed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6967683U JPS5942657U (en) | 1983-05-10 | 1983-05-10 | Reception frequency display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6967683U JPS5942657U (en) | 1983-05-10 | 1983-05-10 | Reception frequency display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5942657U true JPS5942657U (en) | 1984-03-19 |
Family
ID=30199829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6967683U Pending JPS5942657U (en) | 1983-05-10 | 1983-05-10 | Reception frequency display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5942657U (en) |
-
1983
- 1983-05-10 JP JP6967683U patent/JPS5942657U/en active Pending
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