JPS5941885A - Semiconductor laser element - Google Patents

Semiconductor laser element

Info

Publication number
JPS5941885A
JPS5941885A JP15200182A JP15200182A JPS5941885A JP S5941885 A JPS5941885 A JP S5941885A JP 15200182 A JP15200182 A JP 15200182A JP 15200182 A JP15200182 A JP 15200182A JP S5941885 A JPS5941885 A JP S5941885A
Authority
JP
Japan
Prior art keywords
layer
gaas
doped
semiconductor laser
current blocking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15200182A
Other languages
Japanese (ja)
Inventor
Takuo Takenaka
卓夫 竹中
Shinji Kaneiwa
進治 兼岩
Morichika Yano
矢野 盛規
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP15200182A priority Critical patent/JPS5941885A/en
Publication of JPS5941885A publication Critical patent/JPS5941885A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/223Buried stripe structure
    • H01S5/2232Buried stripe structure with inner confining structure between the active layer and the lower electrode

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  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To eliminate the adverse effects caused by a current blocking layer wherein Te is doped and to impart long life operation characteristics, by adding a GaAs buffer layer on a Te doped N<+> GaAs current blocking layer. CONSTITUTION:On a Zn doped P<+> GaAs substrate 21, a current blocking layer 22 comprising Te doped N<+> GaAs is grown by a liquid phase epitaxial growing method. Then a buffer layer 23 comprising undoped GaAs or Si doped N<-> GaAs is grown. Thereafter, a stripe shaped groove 24 is etched from the buffer layer 23 to the substrate 21. Then, a first clad layer 25, an active layer 26, a second clad layer 27, and a cap layer 28 are sequentially deposited by the liquid phase epitaxial growing method again. Thereafter a P type electrode 29 and an N type electrode 30 are evaporated and formed. Then the wafer is divided with the stripe groove 24 as the center, and the end surface of a resonator is formed by a cleaving method.

Description

【発明の詳細な説明】 〈発明の技術分野〉 本発明は半導体レーザ素子に関し、特に基板に電流狭窄
用チャネル溝を形成したC3lS(Ch=annele
d  5ubstrate  Inner  5tri
pe)レーザの素子構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor laser device, and particularly to a C31S (Ch=annele) in which a channel groove for current confinement is formed in a substrate.
d 5ubstrate Inner 5tri
pe) Concerning the element structure of a laser.

〈従来の技術〉 基板にチャネル溝を形成した半導体レーザ素子としては
、第1図に示すようなC3P(Chan−neled 
 5ubstrate  Planer)構造のレーザ
素子が知られている。この半導体レーザ素子は、。−G
aAs基板1のエピタキシャル成長面をエツチング加工
してストライブ状の溝2を形成し、この上にn−GaA
tAsクラッド層3を上面が平坦になるように成長させ
た後、GaAs活性層4、p−GaAtAsクラッド層
5、n−GaAs電流阻止層6を順次積層した後にこの
n−GaAs電流阻止層6にZn等を拡散してp −Q
aAs拡散層7を電流通路として形成し、更にn−Ga
As基板1裏面にn側電極8、p+−拡散層7上にp側
電極9を形成したものである。活性層4は溝2直上部分
でレーザ動作が行なわれ、層厚の薄いn−クラッド層3
に接する部分では活性層4の光がn−GaAs基板1に
しみ出す導波機構が構成されているため、適当な駆動電
流範囲に於いて縦横ともに完全な単一モードのレーザ発
振を行なうことができる。しかしながら、第1図に矢印
で示す如く上記構造の半導体レーザ素子は活性層近辺に
電流の通路幅を規制電流の増加を招くこととなる。
<Prior art> As a semiconductor laser device in which a channel groove is formed in a substrate, a C3P (Chan-neled laser diode) as shown in FIG.
2. Description of the Related Art A laser device having a five-layer planar structure is known. This semiconductor laser element is. -G
The epitaxial growth surface of the aAs substrate 1 is etched to form stripe-shaped grooves 2, and the n-GaA
After growing the tAs cladding layer 3 so that its top surface is flat, a GaAs active layer 4, a p-GaAtAs cladding layer 5, and an n-GaAs current blocking layer 6 are sequentially laminated. By diffusing Zn etc., p −Q
The aAs diffusion layer 7 is formed as a current path, and the n-Ga
An n-side electrode 8 is formed on the back surface of the As substrate 1, and a p-side electrode 9 is formed on the p+- diffusion layer 7. In the active layer 4, the laser operation is performed directly above the groove 2, and the thin n-cladding layer 3
Since a waveguide mechanism is constructed in which the light from the active layer 4 seeps into the n-GaAs substrate 1 at the part in contact with the n-GaAs substrate 1, complete single-mode laser oscillation can be performed both vertically and horizontally within an appropriate drive current range. can. However, as shown by the arrows in FIG. 1, the semiconductor laser device having the above structure causes an increase in the current that restricts the current path width in the vicinity of the active layer.

第2図は上記問題点に鑑み、無効電流を抑制するため内
部ストライブ構造を導入した半導体レーザ素子を示す構
成図である。
FIG. 2 is a configuration diagram showing a semiconductor laser device in which an internal stripe structure is introduced in order to suppress reactive current in view of the above problems.

この半導体レーザ素子は、導波機構が第1図のC8P構
造と同一であるが、n型基板1の代りにp−GaAs基
板11を使用し、p −GaAs基板11上にn−Ga
As電流阻止層12を介在させている。
This semiconductor laser device has the same waveguide structure as the C8P structure shown in FIG. 1, but uses a p-GaAs substrate 11 instead of the n-type substrate 1, and
An As current blocking layer 12 is interposed.

この電流阻止層12の介在により図中に矢印で示す如く
電流阻止層12が除去された溝2に対応する電流の通過
幅はチャネルの両側部分で規制され、横方向への拡がシ
がなくなり無効電流の増加が抑制される。このような構
造はC3lS構造と称される。
Due to the presence of the current blocking layer 12, the current passing width corresponding to the groove 2 from which the current blocking layer 12 has been removed is regulated at both sides of the channel, as shown by the arrow in the figure, and the current does not spread in the lateral direction. Increase in reactive current is suppressed. Such a structure is called a C31S structure.

しかしながら、上記電流阻止層12はn型子、鈍物とし
てTeが用いられ、キャリア濃度が5×1018 3程
度に高濃度のTeをドープしたn+−GaAsから成る
電流阻止層12(厚さ約0.6μm)上にレーザ発振用
多層結晶即ちp−GaAtASクラッド層3′、活性層
4 、n−GaAtAsクラッド層5′、及びn−Ga
Asキャップ層13を成長させるため、この多層結晶層
にTeの影響が現われ、多数のラメラパターンやプレシ
ビテイト等の欠陥が発生する。一般にTe ドープ層上
にエビタギンヤル成長層を形成する場合にはバッファ層
を介在させて結晶回復を図ることが行なわれるが、第2
図の如きC5IS構造では厚さ約0.2μm8度のp−
GaAtAsクラッド層3′シか成長させられないため
、このクラッド層3′を上記バッファ層として兼用する
と層厚の関係で活性層4に達するまでにTeの悪影響を
充分に回復することができなくなって活性層4の結晶性
が阻害されることとなシ、素子特性及び動作寿命の低下
を防ぐことができない。
However, the current blocking layer 12 is made of n+-GaAs (with a thickness of approximately 0 .6 μm), a multilayer crystal for laser oscillation, that is, a p-GaAtAS cladding layer 3', an active layer 4, an n-GaAtAs cladding layer 5', and an n-Ga
In order to grow the As cap layer 13, the influence of Te appears on this multilayer crystal layer, and many defects such as lamella patterns and prechibitates occur. Generally, when forming an evitaginal growth layer on a Te doped layer, a buffer layer is interposed to achieve crystal recovery.
In the C5IS structure as shown in the figure, the p-
Since only the GaAtAs cladding layer 3' can be grown, if this cladding layer 3' is also used as the buffer layer, it will not be possible to sufficiently recover the adverse effects of Te by the time it reaches the active layer 4 due to the layer thickness. If the crystallinity of the active layer 4 is inhibited, deterioration of device characteristics and operating life cannot be prevented.

〈発明の目的〉 本発明は上述の問題点に鑑み、技術的手段を駆使するこ
とによりTeのドープされた電流阻止層に起因する悪影
響を解消し、長寿命の動作特性を付与した新規有用なC
8IS構造半導体レーザ素1を提供するととを目的とす
るものである。
<Object of the Invention> In view of the above-mentioned problems, the present invention provides a novel and useful method that eliminates the adverse effects caused by Te-doped current blocking layers and provides long-life operating characteristics by making full use of technical means. C
An object of the present invention is to provide a semiconductor laser element 1 with an 8IS structure.

〈実施例〉 以下、本発明を実施例に従って図面を参照しながら詳説
する。
<Example> Hereinafter, the present invention will be explained in detail according to an example with reference to the drawings.

第3図は本発明の1実施例を示す半導体C−ブザ素子構
成図である。寸た第4図(A)(B)(C)(D)は第
3図に示す半導体レーザ素子の製造工程図である。
FIG. 3 is a block diagram of a semiconductor C-buzzer element showing one embodiment of the present invention. 4(A), 4(B), 4(C), and 4(D) are manufacturing process diagrams of the semiconductor laser device shown in FIG. 3.

本実施例の半導体レーザ素子は、Teのドープされた信
−GaAs電流阻止層22上にGaAsバッファ層23
を付加したものである。GaAsバッファ層23を堆積
することによシ結晶回復のための層厚が約2倍程度に増
大されるため活性層26への影響が大幅に緩和される。
The semiconductor laser device of this embodiment has a GaAs buffer layer 23 on a Te-doped current-GaAs current blocking layer 22.
is added. By depositing the GaAs buffer layer 23, the layer thickness for crystal recovery is approximately doubled, so the influence on the active layer 26 is greatly alleviated.

また、バッファ層23の導電型をアンドープ又はn−型
とすれば、電流阻止能力及びC8P効果等は従来と同様
に得られる。従って、縦横単一モート”発振に加えて寿
命特性が大きく改善されることとなる。
Furthermore, if the conductivity type of the buffer layer 23 is undoped or n-type, the current blocking ability and the C8P effect can be obtained in the same manner as in the prior art. Therefore, in addition to vertical and horizontal single moat oscillation, the life characteristics are greatly improved.

以下製造工程に従って説明する。The manufacturing process will be explained below.

lX1019−3のキャリア濃度を有するZnドープp
+−Ga l+町基板21上に液相エピタキシャル成長
法により、キャリア濃度5X10’8 −3 を有する
Teドープn4−GaAsからなる電流阻止層22を0
.7μm1さらにアンドープGaA s又はキャリア濃
度lXl0173を有するSiドープn −Gan Asからなるバッファ層(結晶性回復層)23を0.2
μmの厚さに成長させる(第4図(A))。その後バッ
ファ層23よりGaAs基板21に至るまでストライプ
状の溝(チャネル)24をフォトプロセスによりエツチ
ング加工する(第4図(B))。
Zn-doped p with carrier concentration of lx1019-3
A current blocking layer 22 made of Te-doped n4-GaAs having a carrier concentration of 5X10'8-3 is formed on a +-Gal+ substrate 21 by liquid phase epitaxial growth.
.. Furthermore, a buffer layer (crystalline recovery layer) 23 made of undoped GaAs or Si-doped n-Gan As having a carrier concentration of 1Xl0173 is 7 μm1.
It is grown to a thickness of μm (FIG. 4(A)). Thereafter, a striped groove (channel) 24 is etched from the buffer layer 23 to the GaAs substrate 21 by a photo process (FIG. 4(B)).

とのストライプ溝24を300μmのピンチで形成した
後、再度液相エピタキシャル成長法でZnドープp  
Ga□、2A70.BAsからなる第1クラツド25を
層厚0.25μmで、アンドープ’ ” 0.38Ga
0.62P0.78ASO,22から成る活性層26を
層厚0.1μmで、Teドープn−Gao、2At、8
Asから成る第2クラッド層27を層厚1.0μmで、
Teドープn  GaAsから成るキャップ層28を層
厚2μmで、それぞれ順次堆積させる(第4図(C))
o次にp型電極29及びn型電極30を蒸着形成した後
ヌトライブ溝24を中心とする300i、)X μm幅にウェハを分割し、臂開法で共振器端面を形成し
て第3図に示す如き半導体レーザ素子とする0 第5図は本発明の他の実施例を示す半導体レーザ素子の
構成図である。また第6図(AXBXC)(D)は第5
図に示す半導体レーザ素子の製造工程図である。
After forming stripe grooves 24 with a pinch of 300 μm, Zn-doped p
Ga□, 2A70. The first cladding 25 made of BAs is undoped with a layer thickness of 0.25 μm and 0.38 Ga.
The active layer 26 is made of 0.62P0.78ASO,22 with a layer thickness of 0.1 μm, Te-doped n-Gao, 2At, 8
The second cladding layer 27 made of As has a layer thickness of 1.0 μm,
Cap layers 28 made of Te-doped n-GaAs are deposited one after another to a thickness of 2 μm (FIG. 4(C)).
o Next, after forming the p-type electrode 29 and the n-type electrode 30 by vapor deposition, the wafer is divided into 300i, A semiconductor laser device as shown in FIG. 5 is a block diagram of a semiconductor laser device showing another embodiment of the present invention. Also, Figure 6 (AXBXC) (D) is the 5th
FIG. 3 is a manufacturing process diagram of the semiconductor laser device shown in the figure.

本実施例の半導体レーザ素子は結晶性回復の効果をより
一層向上させるためにバッファ層の層厚を厚くしたもの
である。n  −GaAsバッファ層を厚くすることに
よってチャネル溝の深さが1μmを越える結果となり、
従ってp−GaAtAs第1クラッド層の層厚を0.2
5μm程度に設定した場合、このクラッド層で溝を完全
に埋めつくすことは不可能となる。クラッド層厚を厚く
することは単一モード発振の観点よりできないだめ、1
1 −GaA^バッファ層上に更にp−GaAsバッフ
1層を介在させ、このp−GaAsバッファ層で溝を一
部埋めることによシこの上に堆積されるクラッド層の上
鹿毛平坦化して“る・このような構造にすれば電流狭窄
効果は若干劣るが、本来のC8P効果に変化はなく、更
に一層の長寿命化が期待される。
In the semiconductor laser device of this example, the thickness of the buffer layer is increased in order to further improve the effect of crystallinity recovery. By increasing the thickness of the n-GaAs buffer layer, the depth of the channel groove exceeds 1 μm,
Therefore, the layer thickness of the p-GaAtAs first cladding layer is set to 0.2
When the thickness is set to about 5 μm, it becomes impossible to completely fill the groove with this cladding layer. It is not possible to increase the cladding layer thickness from the viewpoint of single mode oscillation, so 1
By further interposing one p-GaAs buffer layer on the 1-GaA^ buffer layer and partially filling the groove with this p-GaAs buffer layer, the top of the cladding layer deposited thereon is flattened. - If such a structure is used, the current confinement effect will be slightly inferior, but the original C8P effect will not change, and even longer life is expected.

以下製造工程に従って説明する。The manufacturing process will be explained below.

lXlO193のキャリア濃度を有するZn ドQ胃 一プp−GaAs基板31上に液相エビタキソヤル成長
法により、キャリア濃度5X1018 3を0η 有するTeドープn”’−GaAsからなる電流阻止層
32を層厚0.7μm1さらにアンドープGaAs又は
キャリア濃度lXl017 3を有するSiドープn 
−GaAsからなる第1バッファ層33を0.4μmの
厚さに成長させる。その後バッファ層33よりQaAs
基板31に至るストライプ状の溝34を深さ1.5μm
までホトエツチング技術で加工する。ここで溝34の深
さを1.5μmと深くしたのは、液相成長の層厚のバラ
ツキによるチャネルの不導通をなくすためと、後続する
2度目の成長で導入するp−GaAsバッファ層35に
よるチャネル(溝)の埋り具合を適当にするためである
On a Zn-doped p-GaAs substrate 31 having a carrier concentration of 1XlO193, a current blocking layer 32 made of Te-doped n"'-GaAs having a carrier concentration of 5X10183 and 0η is formed with a thickness of 0 by the liquid phase epitaxy growth method. .7 μm1 additionally undoped GaAs or Si doped n with carrier concentration lXl0173
- A first buffer layer 33 made of GaAs is grown to a thickness of 0.4 μm. After that, from the buffer layer 33, QaAs
The striped grooves 34 reaching the substrate 31 have a depth of 1.5 μm.
Processed using photoetching technology. The reason why the depth of the groove 34 is made as deep as 1.5 μm is to eliminate non-conductivity in the channel due to variations in layer thickness during liquid phase growth, and also because of the p-GaAs buffer layer 33 introduced in the subsequent second growth. This is to ensure that the channels (grooves) are filled appropriately.

このストライプ状溝34を300μmのピンチで極成し
た後、再度エピタキシャル成長法でZnドープp−Ga
Asからなる第2バッファ層35を層厚0.1μmで(
この時チャネル中央部の層厚は0.7 〜08 μm 
 )  、 Zn  h’ −ン゛p    G a 
。、  2 A t o、sAsからなる第1クラツド
/1i36を層厚o、25μmでアンドープIn   
Ga   P   As   が0.38   0,6
2  0.78   0.22ら成る活性層37を層厚
o、1μmで、Teドープn−Gao、2A7c)、B
Asからなる第2クラッド層38を層厚1μmで、Te
ドープn+−GaAsからなるキャブ層39を層厚2μ
mで、それぞれ順次成長させる。次にP型電極4o及び
n型電極41を蒸着形成し、ストライプ溝34を中心と
する300μm幅にウェハを分割し、臂開法で共振器端
面を形成して半導体レーザ素子とする。本実施例ではバ
ッファ層厚として0.7μm程度の層厚となり第3図の
実施例の約2倍になっている。
After forming this striped groove 34 with a pinch of 300 μm, Zn-doped p-Ga is grown again by epitaxial growth.
The second buffer layer 35 made of As has a layer thickness of 0.1 μm (
At this time, the layer thickness at the center of the channel is 0.7 to 08 μm.
), Zn h' -n p Ga
. , 2 A t o, the first cladding/1i36 made of sAs is undoped with a layer thickness o of 25 μm.
Ga P As is 0.38 0.6
2 0.78 0.22 with a layer thickness o of 1 μm, Te-doped n-Gao, 2A7c), B
The second cladding layer 38 made of As has a layer thickness of 1 μm and is made of Te.
The cab layer 39 made of doped n+-GaAs has a layer thickness of 2μ.
m, and each is grown sequentially. Next, a P-type electrode 4o and an n-type electrode 41 are formed by vapor deposition, and the wafer is divided into 300 μm wide pieces centering on the stripe groove 34, and resonator end faces are formed by the arm-opening method to produce a semiconductor laser device. In this embodiment, the buffer layer thickness is approximately 0.7 μm, which is approximately twice that of the embodiment shown in FIG.

〈発明の効果〉 本発明によれば、Teをド−プしたn型層をチャネル溝
周囲に電流阻止層として介設した場合でも、Te ドー
プ層による悪影響が活性層に及ぶことがなく、従って結
晶性の良好な活性層を形成することかでき素子特性及び
寿命特性を良好に維持することができる。
<Effects of the Invention> According to the present invention, even when a Te-doped n-type layer is interposed around the channel trench as a current blocking layer, the Te-doped layer does not have an adverse effect on the active layer. An active layer with good crystallinity can be formed, and device characteristics and lifetime characteristics can be maintained well.

【図面の簡単な説明】[Brief explanation of the drawing]

第4図は従来のC8P構造半導体レーザ素子の構成図で
ある。 第2図は本発明の基礎となるC5IS構造半導体レーザ
素子の構成図である。 第3図は本発明の1実施例を示す半導体レーザ素子の構
成図である。 第4図(A) (B) (C) (D)は第3図に示す
半導体レーザ素子の製造工程図である。 第5図は本発明の他の実施例を示す半導体レーザ素子の
構成図である。 第6図(A) (B) (C) (D)は第5図に示す
半導体レーザ素子の製造工程図である。 21.31・・・p+−GaAs基板 22.32−電
流阻止層 23.33・・・n  −GaAsバッファ
層26、、.37−・・活性層 35 ・・・p −G
aAsバッフ7層 ′ 代理人 弁理士 福 士 愛 彦(他2名)第5図
FIG. 4 is a block diagram of a conventional C8P structure semiconductor laser device. FIG. 2 is a block diagram of a C5IS structure semiconductor laser device, which is the basis of the present invention. FIG. 3 is a configuration diagram of a semiconductor laser device showing one embodiment of the present invention. 4(A), (B), (C), and (D) are manufacturing process diagrams of the semiconductor laser device shown in FIG. 3. FIG. 5 is a configuration diagram of a semiconductor laser device showing another embodiment of the present invention. 6(A), 6(B), 6(C), and 6(D) are manufacturing process diagrams of the semiconductor laser device shown in FIG. 5. 21.31...p+-GaAs substrate 22.32-current blocking layer 23.33...n-GaAs buffer layer 26, . 37-...Active layer 35...p-G
aAs buffer 7 layers ′ Agent Patent attorney Aihiko Fukushi (and 2 others) Figure 5

Claims (1)

【特許請求の範囲】[Claims] 1、P型基板上にTeドープn型電流阻止層を堆積し、
ストライプ状にチャネル溝を電流通路として開通形成し
た半導体レーザ素子に於いて、前記電流阻止層上に結晶
性回復のためのバップア層を重畳したことを特徴とする
半導体レーザ素子。
1. Depositing a Te-doped n-type current blocking layer on a P-type substrate,
1. A semiconductor laser device in which a striped channel trench is opened as a current path, and a buffer layer for restoring crystallinity is superimposed on the current blocking layer.
JP15200182A 1982-08-31 1982-08-31 Semiconductor laser element Pending JPS5941885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15200182A JPS5941885A (en) 1982-08-31 1982-08-31 Semiconductor laser element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15200182A JPS5941885A (en) 1982-08-31 1982-08-31 Semiconductor laser element

Publications (1)

Publication Number Publication Date
JPS5941885A true JPS5941885A (en) 1984-03-08

Family

ID=15530894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15200182A Pending JPS5941885A (en) 1982-08-31 1982-08-31 Semiconductor laser element

Country Status (1)

Country Link
JP (1) JPS5941885A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6157553U (en) * 1984-09-19 1986-04-17
JPS6196791A (en) * 1984-10-17 1986-05-15 Sharp Corp Manufacture of semiconductor element
JPH0219431U (en) * 1988-07-25 1990-02-08

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6157553U (en) * 1984-09-19 1986-04-17
JPS6196791A (en) * 1984-10-17 1986-05-15 Sharp Corp Manufacture of semiconductor element
JPH0219431U (en) * 1988-07-25 1990-02-08

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