JPS5940295B2 - current amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor (hereinafter FE), for example.
An FE with proportional conduction characteristics like a current mirror amplifier, in which the current gain depends on the ratio of the conduction by the main mirror transistor and the conduction by the slave mirror transistor.
Concerning integrated circuits that depend on T.

A current mirror amplifier (hereinafter referred to as CMA) generally includes current-voltage conversion means that generates a voltage according to an input current, and voltage-current conversion means that generates an output current according to the voltage, and each of the conversion means , a coefficient GVC that is independent of the magnitude of the current being amplified and follows each other as temperature changes to give a total amplification gain such that the output-to-input current ratio is equal to J2G over a considerable range of temperature and amplification current. A type of linear inverting current amplifier that exhibits current-voltage characteristics (sometimes non-linear).

In particular, the current-to-voltage conversion means described above consists of a field-effect "main" mirror transistor arranged to pass the applied input current between the drain and the source by means of a feedback connection between the drain and the gate. The input current is converted into a gate-source voltage (VGs) corresponding to the flowing drain-source current.

This generated voltage VGS is applied between the gate and source of at least one "slave" field effect mirror transistor of the same conductivity type as the main mirror transistor. Each slave mirror transistor acts as a voltage-to-current conversion means and forms a current mirror amplifier with the master mirror transistor.
Previously, in various application circuits, FETs were used as master and slave mirror transistors. had the means to do so.

Without this, the VDS of either mirror transistor
The gain coefficient G changes undesirably with a change in . This drawback is known as "channel shortening" and results from the phenomenon in which the effective channel length, and therefore the conductance of the FET, changes with the applied potential across the channel, ie, drain and source. Channel shortening is similar to the "early effect" that appears in bipolar devices, but is more pronounced than the early effect, especially in short channel or high transconductance devices. It is still desirable to use FETs as mirror transistors, even though CMA designs may require additional components to maintain a constant VDS.

A FET does not require an input current to its control or gate electrode. The base current of a bipolar transistor is prone to induce variations in the G-factor due to variations in manufacturing conditions and transistor operating temperature. FETs tend to be wider bandwidth devices than lateral bipolar transistors;
It has a structure in which the output current vs. input voltage characteristics of the master and slave mirror transistors can be easily matched. Therefore, (U.S. Pat. No. 395
By combining a simple CMA using a FET (as described in the specification of No. 3807) with a circuit network that keeps VDs constant (FET < 7), a CMA with a more stable current gain even when the input/output voltage fluctuates. This circuit network has the disadvantage of complicating the CMA and increasing the voltage required by the input/output circuit of the CMA for proper operation. The highly desirable property that the channel can provide clamping with very small excursions in the voltage across it is lost. Therefore, methods have been devised to make the current gain of a simple CMA using FETs independent of variations in its input and output voltages.
Conventional CMAs require a substrate with a uniform impurity concentration or, common in complementary metal oxide semiconductor or CMOS devices, no drain extensions or, if any, a depth below the active surface of the substrate. FETs formed in locally doped regions called wells or potential wells have been used that are shallow compared to the depth of the degenerate drain region.

The drain extension is defined here as a drain region and source region made of a semiconductor material of the same conductivity type as the drain region and source region of the FET, and extending outward from the periphery of the drain region at least on the surface of the substrate on which the FET is arranged. This is a region where the impurity concentration is lower. Drain extensions are commonly used to increase the drain-source breakdown potential of the FET. For example, FETs formed in a typical CMOS digital circuit designed to have a drain-to-source breakdown potential of at least 15 volts must be placed at a depth of 2 volts from the substrate surface.
．． This FET may have a drain region with a surface impurity concentration of 0μ and a surface impurity concentration of 1020 atoms/Cm3, and a drain extension portion with a depth of about 0.5μ from the substrate surface and a surface impurity concentration of 5×1017 atoms/Cm3. Even if the gate electrode is maintained at a constant potential, the drain-source channel current (ID8) varies as VDS changes. For example, N
The FET is formed in a semiconductor region where the impurity concentration gradually decreases from the surface of the substrate toward its center, as in the case of a P-type well in a type substrate, and is provided with a drain extension extending relatively deep into the substrate region. If so, I due to VDSO fluctuation.

It has been discovered that it is possible to form circuits that rely on FETs with proportional conduction characteristics without the need for additional components to compensate for variations in s. Although such a FET structure is known per se, it has not been discovered that it exhibits a DS characteristic that is substantially unaffected by changes in VD8. This unreported phenomenon is surprising and not what would be expected from normal theoretical contrivances. The present invention is implemented in a current amplifier that has an input/output terminal and a common terminal, and the voltages of the input/output terminals are greatly different, and the amplifier has an impurity concentration gradient such that the specific resistance of the material increases toward the inside of the substrate. It is formed by master and slave field effect transistors provided in a semiconductor substrate region having a similar impurity concentration gradient and a relatively deep drain extension having a similar impurity concentration gradient.

Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The circuit shown in FIG.
, Q2 are included.

FETQl has a feedback path 1 between the drain electrode and the gate electrode.
6, and generates a gate-source potential VGS proportional to the drain-source current IDS in response to the input current 11N applied to the terminal 11. This potential VGS is similar to F
It is applied to ETQ2 via electric path 16 as its gate-source potential, producing a current in the drain-source conductive path of FETQ2. This current 10UT appears at the output terminal 12. The drain-to-source current ratio of Q1 to Q2, and thus the current gain of this circuit, is determined by the ratio of the planar dimensions of the channel regions of the two FETs. Ideally, when the gate-source potential is constant, the drain-source current 1DS of the FET is proportional to the channel width W, and inversely proportional to the channel length t between the source and drain regions, that is, IDSOC-. It is true.

As a result, the gain G of the circuit due to Ql and Q2 is ideally given by Gl2=W2tl/Wlt2. Here, subscripts 1 and 2 refer to FETs Ql and Q2, respectively. In FIG. 1, the broken line section 15 indicates the FETQ
1, Q2 shows a region of a semiconductor material having an impurity concentration gradient formed therein.

This impurity concentration is maximum at the surface of the semiconductor substrate and decreases toward the center of the substrate (downward in the drawing) substantially according to a Gaussian distribution function. As an example, FETQ,,
If Q2 is an N-type tunnel device, region 15 is a P-type region provided in a uniformly doped N-type substrate, and the total silicon CM
It is similar to the P-type well used in IOS devices.

Transistor Ql. Black 4 attached to the drain electrode of Q2
The rectangular shapes 14 and 14' indicate that the drain electrode of the FET has an extension, and this drain extension is the region 54 in FIG.
, 56. The drain extension is formed by giving the impurity concentration a maximum at the semiconductor surface as indicated by the straight line 67-67' and providing a general gradient.
The impurity concentration gradient in this extension substantially follows a Gaussian distribution law. The drain extensions 54, 56 are adjacent to the normal drain regions 53, 55 and are connected to the FET channel portions 72, 56.
71 in series with the main conductive path of the FET, that is, the drain-source conductive path.

The cross section of FIG. 2 shows a FET with a common source region 57 in two NMOS devices coupled as a current amplifier, similar to Ql, Q2 of FIG. First and second FET
are the N-type drain region 55 (53) and the N-type drain extension 56 (54) in contact therewith, the P-type channel region 71 (72) between the drain extension and the N-type source region 57, and the gate insulator 65. (61) and a gate electrode 64 (62) extending over the channel region. These two FETs are formed in a single semiconductor region (P-type well) 58 having the impurity concentration gradient provided in an N-type substrate 59 having a uniform impurity concentration. The structure shown in FIG. 2 is a curved N-type FET structure in complementary MOS technology except for the drain extension 54 (56). The structures of the drain region and drain extension can be more precisely described as the drain contact and drain region, respectively.

By definition, the doped region adjacent to the channel region for receiving charge carriers injected from the source region of the FET is the "drain" region, but that function is performed in this invention by the "drain extension". It will be done. Furthermore, since the highly doped region referred to as the "drain region" in this invention is simply a means of making ohmic contact between the extension and the connection electrode, it is more appropriate to call it a drain contact. However, as mentioned above, since it is a conventional practice to designate a region with a high doping concentration as a "drain region" and a region with a low doping concentration as a "drain extension", this specification will also follow this convention. A drain extension 54 (56) in FIG. (55], but is not limited to this form; the drain extension actually completely surrounds the drain area;
It is also possible for the highly doped drain region to simply form ohmic contact with the drain extension. Additionally, extensions can be similarly formed in the FET source region to further enhance the overall performance of the CMA. A current amplifier is formed by an FET in which relatively lightly doped drain extensions that also have an impurity concentration gradient are formed in a semiconductor material that has an impurity concentration gradient so that the concentration gradient follows a Gaussian distribution. It was found that the device works with a significantly improved input/output current transfer function regardless of the potential difference between the input and output terminals.

Furthermore, in order to improve the device, the constants of the structure are fixed to relative values rather than being limited to their specific absolute values. The desired results have been successfully obtained for the determination of two or more constants.

The requirement is that both the drain extension and the semiconductor in which it is provided have an impurity concentration gradient. The Gaussian distribution of the impurity concentration is thought to be due to the manufacturing method, ie, thermal diffusion.Since the dimension of the semiconductor region in the direction perpendicular to its surface is small, it is almost impossible to measure the impurity distribution. It is unclear why the circuit is improved by the combination of a drain extension with a gradient in impurity concentration and the substrate. or the space-heavy region and its associated potential are sufficiently offset to block the channel shortening mechanism from the normal structure (formed in a semiconductor with uniform impurity concentration), or the mechanism is removed from the channel region of the transistor. This seems to be because they appear at a distance. Listing the constants of one embodiment to which the structure of FIG. 2 is applied, the uniform impurity concentration of the uniformly doped N-type substrate 59 is 1 to 2×10 15 atoms/? 3. The depth X2 from the semiconductor surface 67 of the P-type well 58 having an impurity concentration gradient diffused into the substrate 59 is 5μ, and the surface impurity concentration is 2.
．． 6X1016 atoms/CIrL3, this P-type well 58
The depth X1 from the semiconductor surface 67 of the N-type drain extension 54 (56) having an impurity concentration gradient diffused therein is 2.7.
μ, the surface impurity concentration is 1×1017 atoms/Cm3, and the degenerate N-type drain region 5 also provided in the P-type well 68.
The depth X3 from the surface 67 of 3 (55) is 2μ, and the substantially uniform impurity concentration is 1020 atoms/? 3, and all of these constants have a tolerance of at least 10%.

In another embodiment of the invention shown in FIG.
ETQ8 and Q9 are divided into two isolated areas 35.

Although this configuration allows for increased flexibility in the layout of the integrated circuit, the FET-Q8. Q9 must be placed close enough to ensure thermal coupling and to react simultaneously to temperature changes. The FET is shown in Figures 1 and 2.
There is no particular difference in the performance of the circuit between the case where the circuit is formed in a common area as shown in the figure and the case where the circuit is formed divided into separate areas as shown in FIG. The circuit in Figure 4 consists of FETQl
The circuit is the same as that of FIG. 3, except for the addition of source extensions indicated by regions 45 and 45' for O and QlK, respectively.

These source extensions are generally provided for processing convenience, but they provide a low effective negative feedback resistance at the source connection of each transistor to improve circuit linearity. The edges of the FET channel, the inner edges of the regions that will become the effective drain and source regions, are typically formed by a common photomask process for maximum dimensional accuracy. This clearly indicates that the drain region and the source region are formed simultaneously by the same component (drain extension), especially when the channel length is less than a few microns. However, forming a FET with an extension only in the drain region is possible when the dimensional accuracy of the channel length t is lower than that possible in a FET with a source extension and a drain extension.
The dimensional accuracy is 1 to give the required gain G to the current amplifier.
It is a factor. The output FET of the current amplifier, for example, Q in Fig.
By connecting the gate electrode and source electrode of the transistor No. 2 to the gate electrode and source electrode of another transistor, the current amplifier of the above type can be coupled to another output transistor to obtain another independent output current. .
Since the gate electrode of a FET inherently has no current flowing through it, a relatively large number of such transistors can be arranged in parallel, as is known to those skilled in the art. It may be formed in a single semiconductor region together with other transistors, or the semiconductor region may be divided into a plurality of separate regions each containing one transistor. Having described the invention, those skilled in the art will be able to construct other embodiments within the scope of the invention with reference to the above cited patents.For example, transistor Ql.
When Q2 is formed in one semiconductor region, each source region can be formed separately in a common area as shown in FIG.

[Brief explanation of drawings]

1, 3, and 4 are circuit schematic diagrams of three embodiments of the present invention, and FIG. 2 is a sectional view of an integrated circuit structure including one embodiment of the present invention. Q1...First FET (main mirror transistor), Q2...Second FET (submirror transistor), 10...Common terminal, 11...・
Input terminal, 12... Output terminal, 15.58...
...P-type well (first semiconductor region), 53, 55
...Drain area, 54, 56...Drain extension? L57... Source area, 59...
...Substrate, 71, 72...Channel area, X
1... Depth of drain extension.

Claims (1)

[Claims] 1 A current amplifier comprising first and second insulated gate field effect transistors formed in a first semiconductor region having a first impurity type, each of which has a first impurity type; a drain semiconductor region and a source semiconductor region of a second impurity type provided, the first and second impurity types forming regions of opposite conductivity type, and the first transistor as a main mirror transistor. the second transistor is connected between the output terminal of the amplifier and the common terminal to operate as a slave mirror transistor; The current gain is ideally determined by the ratio of the geometric dimensions of the main mirror transistor and the secondary mirror transistor, and the amplifier circuit has a form in which the potential of the input terminal and the potential of the output terminal are different from each other. the first semiconductor region has a diffused impurity concentration gradient having a maximum impurity atomic density at its surface, and a drain extension is provided adjacent to each drain region of the first and second transistors. , these drain extensions are of the second impurity type and have a lower impurity concentration than the drain region, the impurity concentration having a sloped diffusion type distribution with a maximum impurity atomic density at the semiconductor surface. , the drain extension is formed in a conductive channel between the respective drains and sources of the first and second transistors to eliminate channel shortening effects and make the current gain of the amplifier substantially independent of the different potentials. A current amplifier extending sufficiently deeply from the surface of the first semiconductor region into the interior thereof so as to provide a current amplifier.