JPS593975A - Structure of high withstand voltage transistor for write of nonvolatile memory element - Google Patents

Abstract

PURPOSE:To enable the design of withstand voltage, further simplify the constitution of write cells of a nonvolatile memory element, and enable the same treatment for write and erase lines by using high withstand voltage transistors having the same channel structure for impressing high voltages of both polarities positive and negative. CONSTITUTION:An element is formed in a structure wherein stacked gate high withstand voltage transistors A and B are arranged in series. In the case of generating the high potential of positive polarity at a write (erase) terminal 50, when the bias wherewith the high withstand voltage transistor B is conducted is impressed on the control gate terminal 46 of the high withstand voltage transistor B, the source terminal 43 of the high withstand voltage transistor A is kept at an earth potential. When the bias wherewith the high withstand voltage transistor A is cut off is impressed on the control gate terminal 42, the high withstand voltage transistor A maintains a cut-off state, the high potential of positive polarity is impressed on the gate part 49 of the nonvolatile memory element, and accordingly write is enabled, because the design of withstand voltage for the high potential of positive polarity is performed on the drain side.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-voltage transistor structure for writing (erasing) a digital memory element. Generally, EEPROM (also EA ROM), which is a non-volatile memory element that can be electrically written and erased, is made of S i 02-S, which is a two-layer insulating film.
The charging and discharging of carriers at the trap center (capture center) that naturally occurs at the i3N4 interface causes a tunnel or avalanche phenomenon, and volatile memory elements, polycrystalline Si grains, and metal are completely separated with an insulating film. Then, a potential well is forcibly formed on the gate to make it a floating type, and similarly avalanche and Fowler-Nor
writing by causing tunneling phenomenon etc.
A FAMO5 type nonvolatile memory element with a control gate that performs erasing is generally known. Since such electrically programmable EA ROM uses physical phenomena such as tunneling and avalanche breakdown as described above, it is currently possible to write (or erase) data by inducing this phenomenon with a fairly low voltage. However, since it is necessary to provide a potential difference (electric field difference) between writing (erasing) and driving voltage of nonvolatile memory elements, PN
By using means such as bonded substrate isolation, it is necessary to configure a memory cell in which the write (erase) voltage is not affected by on-chip peripheral transistors.

For example, when writing (erasing) using an MNO8 memory element, if we consider a high voltage design with a PN junction voltage using an N-type substrate, if we use an N-channel high voltage transistor, it will be possible to write to a positive polarity high voltage. For negative polarity, voltage resistance design is possible, but voltage resistance design is difficult because the voltage is applied in the forward direction for negative polarity, and a special board separation method must be considered, and writing and erasing lines must be Separation will also be forced.

The present invention eliminates such drawbacks and enables a voltage-resistant design using high voltage suppression transistors having the same channel structure for both positive and negative high voltage applications, and also significantly simplifies the write cell configuration of nonvolatile memory elements. Furthermore, writing and erasing lines can be processed on the same line, which is extremely effective.

This will be explained below according to the drawings. FIG. 1 shows a well-known N-channel stacked gate type high breakdown voltage transistor structure. Here, 1 is an N-type substrate, a plate, 2 is a P-aligned layer, 6 is a field oxide film, 4 is a drain N+ region, and 5 is a source N
+ area, 6 is N- area, 7 is P+ guard ring area, 8
1 is a gate a film, 9 is polysilicon, 10 is a control gate electrode, 11 is an offset gate electrode, 12 is a source electrode, 16 is a drain electrode, and 14 is a P-substrate electrode. In general, a stacked gate type high voltage transistor is composed of a control gate electrode 10 and an offset gate electrode 11 for relieving electric field concentration near the drain 4, and also has a thick oxide film 3 near the drain in the channel. Similarly, by providing an N-I region in the P- region under the thick oxide film 6, the drain breakdown voltage is increased.

The present invention provides a high voltage transistor having such a structure,
By connecting two or more transistors in series, there is provided a high voltage transistor for writing (erasing) a nonvolatile memory element that can withstand high voltages of both positive and negative polarities.

FIG. 2 shows an example of a writing means for a nonvolatile memory element using the stacked gate high voltage transistor. A method is generally used in which an impurity diffusion region terminal (herein referred to as a drain) 11 near the thick oxide film in the channel is short-circuited to a gate terminal 12 of a nonvolatile memory element and connected to a write power supply.

Here, while applying, for example, a positive polarity voltage to the offset gate terminal 15, the source terminal 17 and the substrate terminal 16 are short-circuited and grounded, and the stacked gate high voltage transistor is connected to the control gate terminal 14 until it is turned off. For example, while the control gate terminal 14 is grounded, the drain terminal 11 and the nonvolatile memory element gate terminal 12 are short-circuited and connected to the write voltage source 16. When a high voltage of positive polarity is generated with such biasing, the withstand voltage near the drain region improves due to the effect of relaxing the electric field concentration in the depletion layer region due to the thick oxide film and offset gate bias as described above. It is possible to obtain a breakdown voltage higher than that, and it is possible to apply a high voltage of, for example, +30V to the gate terminal 12 of the nonvolatile memory element, thereby making it possible to write information. However, in such a circuit, it has been difficult to design a withstand voltage because the bias on the drain side exhibits forward characteristics in response to a high voltage of negative polarity.

FIG. 3 shows an embodiment of the invention.

The present invention has a configuration in which stacked gate high voltage transistors A and B are arranged in series, and the drain terminal 41 of the high voltage transistor A is connected to the gate portion 49 of the nonvolatile memory element through a high resistance load 56. and connect to the write (erase) terminal 50.

Furthermore, the source terminal 46 and substrate terminal 44 of the high voltage transistor A are short-circuited, and connected to the drain terminal 45 of the high voltage transistor B, which is short-circuited to the P-substrate terminal 48 . Further, the configuration is such that the booth terminal 47 of the high voltage transistor B is grounded.

Therefore, for example, when generating a high potential of positive polarity at the write (erase) terminal 50, there is a voltage such as +1.5 is applied, the source terminal 46 of the high voltage transistor A is maintained at the ground potential, and the high voltage transistor A is further cut off.
Since the drain side is designed to withstand a high potential of positive polarity as described above, the high voltage transistor A maintains a cut-off state, and the gate portion 49 of the nonvolatile memory element maintains a positive polarity. Considering the case where a high potential of, for example, +30μ is applied to enable writing while generating a high potential of negative polarity, the drain N+ region 64 and P- Since the substrate 61 junction is forward biased, a negative high potential is applied to the drain terminal 45 of the high voltage transistor B, which is short-circuited to the substrate terminal 48 of the high voltage transistor B, via the source terminal 46 of the high voltage transistor A. . On the other hand, when the control gate terminal 46 of the high voltage transistor B is grounded and maintained in a cut-off state, the drain N+ region 66 and the P-substrate 60 are similarly forward biased, so the P-substrate 62 has a negative high voltage. A potential is applied.

However, as mentioned above, the source side of the stacked gate high voltage transistor B can be designed with voltage resistance due to the field oxide film 33's electric field concentration relaxation effect and the offset gate terminal 52's electric field concentration relaxation effect near the source surface. The high voltage transistor B maintains a cut-off state, and a negative high potential can be provided to the gate terminal 49 of the nonvolatile memory element, making it possible to erase the data.

In addition, the offset gate terminals 51 and 52 of the high voltage transistors A and B are connected to the drain terminal 41 and the source terminal 4, respectively.
A similar effect can be obtained even in a short-circuited state to 7.

Therefore, according to the present invention, bipolar high voltages associated with writing and erasing of a nonvolatile memory element are generated through high voltage transistors with the same channel structure, when conventionally generated using substrate isolation such as PN junction isolation. It was very difficult to design, and the structure also had the disadvantage of being complicated.

The present invention simplifies the write cell by connecting two or more inverted N-channel stacked gate structures in series, which have a simple known structure, and furthermore, it is possible to generate bipolar high voltages in the same line processing. It is possible and the effect is extremely strong.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of a high-voltage N-channel star-type transistor. FIG. 2 is a cross-sectional view showing a write connection of a nonvolatile memory element using a high voltage N-channel stacked gate transistor. Figure 3 shows two stacked gate transistors of the present invention.
FIG. 3 is a cross-sectional view showing a write connection of a nonvolatile memory element connected in series. 1.60...N substrate, 2.61.62...P-aligned, 3.66
...field oxide film, 10.14.42...
...Control Kate, 11.15.51.52
...Offset gate, 50...Write (erase) terminal.

Claims (2)

[Claims] (1) A logic circuit including a clock circuit integrated on the same substrate, a display device that displays the time measurement contents of the logic circuit, an electrically writable nonvolatile memory element that provides data to the logic circuit, and An integrated circuit having a write circuit for a non-volatile memory element, characterized in that the write circuit is provided with a high-voltage transistor separated from the non-volatile memory element and the logic circuit by a substrate. High-voltage transistor structure for writing. (2) A logic circuit including a clock circuit integrated on the same substrate, a display device that displays the time measurement contents of the logic circuit, an electrically writable nonvolatile memory element that provides data to the logic circuit, and the nonvolatile In the integrated circuit having a write circuit for a static memory element, the write circuit is provided with a high-voltage transistor separated from the non-volatile memory element and the logic circuit by a substrate, the first and second non-volatile memory elements. A small number of high-voltage transistors are connected in series, connected to a write power supply terminal via a load of the drain electrode of the first high-voltage transistor, and a substrate of the first high-voltage transistor is connected to the write circuit. A source electrode short-circuited to the electric body is short-circuited to a substrate electrode of a second high-voltage transistor, and further connected to a drain electrode of the second high-voltage transistor,
A high voltage transistor structure for writing in a nonvolatile memory element, further comprising a configuration in which a source electrode of the second high voltage transistor is grounded.