JPS5939024A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5939024A
JPS5939024A JP14771582A JP14771582A JPS5939024A JP S5939024 A JPS5939024 A JP S5939024A JP 14771582 A JP14771582 A JP 14771582A JP 14771582 A JP14771582 A JP 14771582A JP S5939024 A JPS5939024 A JP S5939024A
Authority
JP
Japan
Prior art keywords
film
layer
gaas
substrate
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14771582A
Other languages
Japanese (ja)
Other versions
JPH0419700B2 (en
Inventor
Kenya Nakai
中井　建弥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14771582A priority Critical patent/JPS5939024A/en
Publication of JPS5939024A publication Critical patent/JPS5939024A/en
Publication of JPH0419700B2 publication Critical patent/JPH0419700B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02642—Mask materials other than SiO2 or SiN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

PURPOSE:To selectively and excellently form a III-V family compound semiconductor layer on a semiconductor substrate, by employing as a mask a III-family element nitride layer formed on the semiconductor substrate. CONSTITUTION:An aluminum nitride layer 12 is formed on a GaAs substrate 11. After the layer 12 is etched to provide an opening, a GaAs film 13 is grown on the substrate 11. The growth of the film 13 with the layer 12 used as a mask permits the film 13 on the mask not to mention the substrate 11 to be formed substantially flat. It is to be noted that the III-family element nitride is required to be amorphous, polycrystalline or single crystal. An equivalent effect can be obtained with a III-V family compound semiconductor.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明は■−Ｖ族化合物半導体を半導体基板上に選択的
に形成させる方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for selectively forming a ■-V group compound semiconductor on a semiconductor substrate.

（２）従来技術と問題点 従来、ＭＯ−ＣＶＤ　（Ｍｅｔａｌ　Ｏｒｇａｎｔｚａ
ｔｉｏｎ　ＣｈｅｍｌｃａｌＶａｐｏｒ　Ｄｅｐｏｓｉ
ｔｉｏｎ　（有機金属気相成長））法によって、■−Ｖ
族化合物半導体、例えばガリウム・ヒ素（ＧａＡｓ　）
　、ガリウム・アルミニウム・ヒ素（ＧａＡｔＡｓ）等
を半導体基板上にエピタキシャル成長せしめる場合、絶
縁膜として二酸化シリコン（８１０２）膜がよく用いら
れており、Ｓ　ｔ　Ｏ２膜上では、ＧａＡｓ　ｒ　Ｇａ
ＡｔＡｓは粒子状の多結晶の集合体として析出すること
が知られている。第１図は従来技術を説明するための概
略断面図であυ、ＧａＡｓ基板１上に形成された開口を
有する５ＩＯ２膜２を選択マスクとしてＧａＡｓ層３を
ＣＶＤ成長せしめた図が示されている。第１図によれば
、５ＩＯ２膜２上の開口近傍（第１図のＡ部）において
は粒子状のＧａＡｓの成長密度が低下し、一方マスク近
傍の選択成長部分即ち開口内のエツジ部分（第１図のＢ
部）においてはＧａＡｓ層３の厚さが異常に大きく成長
していることがわかる。すなわちｘｏｏｏｏ（１３程度
以上の厚膜の選択成長は平坦性が損なわれてイ、Ｘ、。(2) Conventional technology and problems Conventionally, MO-CVD (Metal Organza
tion Chemical Vapor Deposit
tion (metal-organic vapor phase epitaxy)) method,
Group compound semiconductors, such as gallium arsenide (GaAs)
, gallium aluminum arsenide (GaAtAs), etc., on a semiconductor substrate, a silicon dioxide (8102) film is often used as an insulating film, and on a S t O2 film, GaAs r Ga
It is known that AtAs is precipitated as a particulate polycrystalline aggregate. FIG. 1 is a schematic cross-sectional view for explaining the prior art, and shows a GaAs layer 3 grown by CVD using a 5IO2 film 2 having an opening formed on a GaAs substrate 1 as a selective mask. . According to FIG. 1, the growth density of particulate GaAs decreases near the opening on the 5IO2 film 2 (section A in FIG. B in Figure 1
It can be seen that the thickness of the GaAs layer 3 has grown abnormally large in part). That is, xoooo (selective growth of a thick film of about 13 or more will result in loss of flatness).

この上記２つの問題が、フォトリソグラフだ、緻密な層
が得られない為、エツチングが不均一となったりエツチ
ング液が残留するという問題を生じる。第２図はＭＯ−
ＣＶＤ法によりＧａＡｓを５１０２膜上に成長させた場
合の多結晶粒子数と、原料であるＴＭＧ（トリメチルガ
リウム（（ＣＨ３）５Ｇａ））濃度との関係を示したグ
ラフであり、第２図から、５１０２膜上ではＴＭＧの濃
度を低くするとＧａＡｓ基板の多結晶粒子の密度は低く
なるカーはとんどＴＭＧ濃度が０に近い場合にのみ粒子
の核の形成が０になることがわかる。そしてこの核の形
成量は、成長温度を変化させたり、ガス流速に変化を与
えてもあ１り変化はない。従って、上記選択成長部分の
異常成長の問題と合わせて５１０２膜は基板上にＩ−Ｖ
族化合物半導体を選択的に成長させる際のマスク材料と
して不適当である。These two problems arise in photolithography, where a dense layer cannot be obtained, resulting in non-uniform etching and residual etching solution. Figure 2 shows MO-
This is a graph showing the relationship between the number of polycrystalline particles when GaAs is grown on a 5102 film by the CVD method and the concentration of the raw material TMG (trimethyl gallium ((CH3)5Ga)). On the 5102 film, when the TMG concentration is lowered, the density of polycrystalline grains on the GaAs substrate is lowered. Kerr shows that the formation of grain nuclei becomes zero only when the TMG concentration is close to zero. The amount of these nuclei formed does not change even if the growth temperature is changed or the gas flow rate is changed. Therefore, in addition to the problem of abnormal growth in the selectively grown portion mentioned above, the 5102 film is
It is unsuitable as a mask material when selectively growing group compound semiconductors.

（３）発明の目的 そこで上記欠点を鑑み本発明の目的は■−ｖ族化合物を
半導体基板上に選択的に良好に形成させるための半導体
装置の製造方法を堤供することである。(3) Purpose of the Invention In view of the above-mentioned drawbacks, the purpose of the present invention is to provide a method for manufacturing a semiconductor device in which a ■-v group compound can be selectively and satisfactorily formed on a semiconductor substrate.

（４）発明の構成 本発明の目的は半導体基板上に形成されだ■族元素窒化
物層をマスクとして該半導体基板上に■−■族化合物半
導体層を選択的に形成することにより達成される。(4) Structure of the Invention The object of the present invention is achieved by selectively forming a group ■-■ compound semiconductor layer on a semiconductor substrate using a group III element nitride layer formed on the semiconductor substrate as a mask. .

尚、前記■−■族半導体を選択的に形成させる場合のマ
スク材料としてアモルフォス状又は多結晶あるいは、単
結晶状の■族元素窒化物を用いる。Incidentally, an amorphous, polycrystalline, or single-crystalline group (II) element nitride is used as a mask material when selectively forming the above-mentioned (1)-(2) group semiconductor.

（５）発明の実施例 以下本発明の実施例を図面に基づいて詳細に説明する。(5) Examples of the invention Embodiments of the present invention will be described in detail below based on the drawings.

第３図は本発明に係る実施例を示す概略断面図である。FIG. 3 is a schematic sectional view showing an embodiment according to the present invention.

本発明によれば、第３図に示すように、ＧａＡｓ基板１
１上にス／ｆツタ法によって厚さ２０００〔Ｘ〕の窒化
アルミニウム（ＡｔＮ）層１２を形成する。そして熱燐
酸（Ｈ３ＰＯ４）をエッチャントとして用いた選択エツ
チング法によって該ＡｔＮ層１２をエツチングして該Ａ
ｔＮ層１２に開口を設けた後、ＴＭＧ（（ＣＲ２）　３
Ｇ＆　）とＡｓＨ，とＨ２ガスを用いてＭＯ−ＣＶＤ法
によって成長速度が０．２〔ｚｚｚ分〕で、１０分間の
成長条件下でＧ　＠Ａ　ｓ膜１３をＧａＡｓ基板１１上
に成長させる。第３図から明らかなように本実施例よう
にＡｔＮ層１２をマスクとしてＧａＡｓ膜１３全１３さ
せると、ＧａＡｓ基板１１上は勿論、マスク上のＧａＡ
ｇ膜１３もはソ平坦性よく形成される。すなわち従来発
生したような、選択成長部分、即ち開口内のエツジ部分
でのＧａ　Ａ　ｓの異常成長は生ぜず、又ＡｔＮ膜１２
、即ちマスク層上の開口近傍に於いても粒子形成の低密
度化を生じなかった。ＡｔＮ層１層上２上ａＡｓ膜１４
の絶縁性を測定したところ１０９〔Ω・ｍ〕であった。According to the present invention, as shown in FIG.
An aluminum nitride (AtN) layer 12 having a thickness of 2000 [X] is formed on the substrate 1 by the S/F ivy method. Then, the AtN layer 12 is etched by a selective etching method using hot phosphoric acid (H3PO4) as an etchant.
After providing an opening in the tN layer 12, TMG((CR2) 3
A G@As film 13 is grown on the GaAs substrate 11 by MO-CVD using G&), AsH, and H2 gas at a growth rate of 0.2 [zzz minutes] for 10 minutes. As is clear from FIG. 3, when the entire GaAs film 13 is formed using the AtN layer 12 as a mask as in this embodiment, not only the GaAs substrate 11 but also the GaAs film 13 on the mask is exposed.
The g film 13 is also formed with good flatness. That is, abnormal growth of GaAs does not occur in the selectively grown portion, that is, the edge portion within the opening, as has conventionally occurred, and the AtN film 12
That is, even in the vicinity of the openings on the mask layer, the density of particles did not decrease. AtN layer 1 upper layer 2 upper aAs film 14
When the insulation property was measured, it was 109 [Ω·m].

ＡｔＮ層１層上２上多結晶粒子の核生成の密度が８１０
２膜上の場合より数桁以上大きいため緻密なＧａＡＩＩ
膜が成長したものと考えられる。又従来用いられていた
５Ｓ０２膜けＧａＡｌ！　との親和性が小さいがＡｔＮ
等の■族元素窒化物とＧａＡｓとの親和性はある程度大
きいために均一に核生成が起こるものと考えられる。な
お■族元素窒化物はアモルフォス又は多結晶又は単結晶
状であることが必要である。なぜならｋｔＮ等窒化物上
の成長層は絶１禄性であることが必要だからである。又
本発明ではＧ　ａ　ＡＢ膜の成長のみについて述べてい
るがＩＩ　−Ｖ族化合物半導体例えばＧａＡｔＡｓ　、
ＩｎＧａＡｓ、等でも同じ効果が得られることは容易に
理解されよう。The density of nucleation of polycrystalline particles on AtN layer 1 and layer 2 is 810
GaAII is dense because it is several orders of magnitude larger than that on two films.
It is thought that a film has grown. Also, the conventionally used 5S02 film GaAl! Although the affinity with AtN is small,
It is thought that nucleation occurs uniformly because the affinity between group Ⅰ element nitrides and GaAs is relatively high. Incidentally, the group Ⅰ element nitride needs to be amorphous, polycrystalline, or single crystalline. This is because a layer grown on a nitride such as ktN needs to be irresistible. Furthermore, although the present invention describes only the growth of a Ga AB film, it is possible to grow a II-V group compound semiconductor such as GaAtAs,
It will be easily understood that the same effect can be obtained with InGaAs, etc.

（６）発明の詳細 な説明したように本発明に係る方法によれば半導体素子
形成可能な平坦な■−Ｖ族化合物半導体が選択的に形成
される。(6) Detailed Description of the Invention As described above, according to the method of the present invention, a flat 1-V group compound semiconductor capable of forming a semiconductor device is selectively formed.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来技術を説明するための概略断面図であり、
第２図はトリメチルガリウム（ＴＭｃ）ａ度とＧａＡｐ
多結晶粒子数との関係を示すグラフであり、第３図は本
発明に係る実施例を示す概略断面図である。 １・・・ＧａＡｓ基板、２・・・５１ｏ２膜、３・・・
選択成長ＧａＡｓ　、　４−多結晶ＧａＡｓ　％　１１
−ＧａＡｓ基板、１２・・・ＡｔＮ層、１３・・・選択
成長ＧａＡｓ、１４・・・多結晶ＧａＡｓ　０FIG. 1 is a schematic sectional view for explaining the conventional technology,
Figure 2 shows trimethyl gallium (TMc) a degree and GaAp.
It is a graph showing the relationship with the number of polycrystalline particles, and FIG. 3 is a schematic cross-sectional view showing an example according to the present invention. 1...GaAs substrate, 2...51o2 film, 3...
Selective growth GaAs, 4-polycrystalline GaAs% 11
-GaAs substrate, 12...AtN layer, 13...selectively grown GaAs, 14...polycrystalline GaAs 0

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成された■族元素窒化物層をマスクと
して該半導体基板上に■−ｖ族化合物半導体層を選択的
に形成することを特徴とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device, comprising selectively forming a group 1-V compound semiconductor layer on a semiconductor substrate using a group 1 element nitride layer formed on the semiconductor substrate as a mask.
JP14771582A 1982-08-27 1982-08-27 Manufacture of semiconductor device Granted JPS5939024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14771582A JPS5939024A (en) 1982-08-27 1982-08-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14771582A JPS5939024A (en) 1982-08-27 1982-08-27 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5939024A true JPS5939024A (en) 1984-03-03
JPH0419700B2 JPH0419700B2 (en) 1992-03-31

Family

ID=15436555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14771582A Granted JPS5939024A (en) 1982-08-27 1982-08-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5939024A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219616A (en) * 1986-03-20 1987-09-26 Oki Electric Ind Co Ltd Method for crystal growth of gaas
JPH0462917A (en) * 1990-07-02 1992-02-27 Hikari Gijutsu Kenkyu Kaihatsu Kk Selective growth method of compound semiconductor
JPH05121328A (en) * 1991-10-28 1993-05-18 Hikari Gijutsu Kenkyu Kaihatsu Kk Compound semiconductor epitaxial growth method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161265A (en) * 1974-11-25 1976-05-27 Handotai Kenkyu Shinkokai 335 zokukagobutsuhandotaisoshi

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161265A (en) * 1974-11-25 1976-05-27 Handotai Kenkyu Shinkokai 335 zokukagobutsuhandotaisoshi

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219616A (en) * 1986-03-20 1987-09-26 Oki Electric Ind Co Ltd Method for crystal growth of gaas
JPH0462917A (en) * 1990-07-02 1992-02-27 Hikari Gijutsu Kenkyu Kaihatsu Kk Selective growth method of compound semiconductor
JPH05121328A (en) * 1991-10-28 1993-05-18 Hikari Gijutsu Kenkyu Kaihatsu Kk Compound semiconductor epitaxial growth method

Also Published As

Publication number Publication date
JPH0419700B2 (en) 1992-03-31

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