JPS5937600A - Voice sintax repetition sender - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an audio sentence repetition sending device in which the number of spellings and the spelling interval can be arbitrarily set.

Conventionally, as shown in FIG. 1, an audio sentence repetition transmitting device has a memory fis1it unit 2 that reads out the contents of an audio memory 6 while referring to a broadcasting table stored in a memory 4). analog) converter 8 D/A
There are some that are converted and emitted from the Nupica 10.

This device for repeatedly transmitting audio literature has a drawback in that the number of repeats and repeat intervals are determined by the broadcast table stored in the memory 4, and it is not possible to set an arbitrary number of repeats and repeat intervals.

In this invention, the number of repetitions and the interval of repetition n1 are arbitrary vc.
We propose a device for repeatedly transmitting audio sentences that can be set in stages! It is an attempt to deviate from this.

The present invention will be explained below based on an illustrated embodiment.

In Fig. 2, 20) 22% 24 is an input section into which numbers [A, ESC (both positive integers)] specifying the sentence to be broadcast, the number of re-spellings, and the repetition interval are input, and 26 is the input section for this audio sentence. Repetitive delivery device'.

This is an input section into which an activation signal for activating the is input.

The numerical value A input to the input part zO is supplied to the latch 28, and the number 8i:C14 input to the input part 22 is supplied to the input terminal of the counter 32 via the buffer 30, and then the input part 24 is supplied to the input terminal of the counter 32. The @value C that is input to the latch 34 can be supplied to the latch 34.

Now, if a start signal is input to the input section 26, this start fr SJ is supplied to the launches 2B, 34, the low l''A11ir of the counter 32, and the OR circuit 36TIc.

By kneading, Lunch 28 maintains the numerical value A and Bunbe 7.
Number A]-Response conversion circuit 38t/c supplies numerical value A.

The text number 5/address conversion circuit 38 converts this numerical value A into the sound j
ii One of the plurality of sentences stored in memory 40 is converted into a designated address and supplied to the voice memory control section 4.4vc.

^ Also, the counter 32 initializes the numerical value B to fj by the X start signal.
'rf, read as B The latch 54 holds the numerical value C by the activation signal and supplies the numerical value C to the counter 42.

The activation signals σ and others are supplied to the memory control circuit 44 via the 1-OR circuit 36 with a slight delay.

The activation signal supplied to the memory control circuit 44 is as shown in FIG. When the output terminal becomes a low level, the clock pulse generation circuit 62 generates a clock pulse, and supplies this clock pulse to the parallel counter circuit 66 via the buffer 64.The parallel counter circuit 66 is connected in parallel to the The five via counters 68D to 68e count clock pulses to generate a via count signal, which is input to a decoder 72 in the audio memory 40 via a buffer circuit 70.

The audio memory 40 has sentences stored in a predetermined number of addresses each starting from a plurality of addresses specified by the sentence number address conversion circuit 38, and the decoder 72
In accordance with the reverse signal supplied from the buffer circuit 70, the text address conversion circuit 38vc converts the text information stored from the designated address to a predetermined number of subsequent addresses. 46vc order, and the sound is emitted from Nupica 48.

Furthermore, the memory control circuit 44vc is supplied σJ via the OR circuit 36, and the activation [d8.
reads the numerical value C that can be supplied from the latch 34 as the initial value C.

Next, when the transmission of the sentence t is completed and the 1-byte large counter 68e generates a single output, this carry output is sent to J via the counter 32, timer 50 and NOR circuit 74.
It is supplied to the K flip-flop processor 0 and the BCD counter 68D to 68(σ) clear terminal.

As a result of the kneading, the 01 output terminal of the JK flip-flop 60 becomes high level, the operation of the 1-clock pulse generating circuit 62 is stopped, and the four large counters 68a to 680 are reset.

In addition, when the carry output is supplied, the counter 32 counts down the count output by one and outputs the count output to the 0 judgment circuit 5.
Since the current count output is the initial value 13, when a carry output occurs, the 1.゛ circuit 78 and J
The memory control IU circuit 44 is composed of a K flip-flop 80, and the start signal is inputted to the input section 26 again after the counting output of the counter 32 becomes 0.
Since B-1 is not O at present, the stop message J is not sent.

Further, when a carry output is supplied from the timer 50 memory control circuit 44, an output is generated every seven seconds for a fixed period of time (1 s), and this output is supplied to the counter 42B7 (jjH. This output is supplied by I
The count output subtracted by Jfvx is sent to the O determination circuit 54.

1)×C seconds after the start signal is supplied to the timer 50, the count output of the counter 42 becomes O, and when the output of the counter 42 becomes O[, the 0 judgment circuit 54 that generates the start output outputs the start output. to circuit 36 and timer 50. Note that the 0 determination circuit 54 is constituted by an all-input NAND circuit.

When the timer 50 knows that the starting output can no longer be supplied, the generation of the output is stopped δ. Further, the OR circuit 36 is connected to the memory control section 4
4 and the load terminal of the counter 42 send out this activation output, and the second transmission of the designated sentence is started by the sentence number address conversion circuit 38 in the same way as when the initial signal was inputted. At the same time, the value C is displayed on the counter 42.
Load it. Therefore, after one vocalization, tX
The next sound emission is started after an interval of C seconds.

Thereafter, the same operation is repeated until the sending of the eighth sentence is completed, and the memory control 1 circuit 44 transfers the carry output to the counter 3.
2 and the timer 50, the count output of the counter 32 becomes 0. As a result, the 0 determination circuit 52 supplies a stop signal to the memory control circuit 44, and the memory control circuit 44 is prevented from receiving a start signal and a start output.

At the same time, the timer 50 is activated by the end signal, and the 0 discriminator circuit supplies a startup output to the OR circuit 36vc after tXC seconds by the above-described operation, but as described above, this is not accepted by the memory control circuit 44, and the timer 50 stops and completes all operations. Therefore, one sound emission is repeated B times.

As explained above, according to the present invention, the timer 50, which is activated every time the sound emission ends, counts down the output generated every predetermined time using the counter 42, and when the count reaches 10, the sound emission is started again. The counter 32 receives a signal generated by the memory control circuit 44 every time the h9 voice ends.
Countdown 1. Since the system is configured to stop broadcasting when OC is reached, the number of repetitions and repetition interval can be set arbitrarily by changing the number of repetitions and the repetition interval set in the counter 32.42. It is possible to realize an audio sentence repetition transmission device F (which can flexibly respond to such uses).

In the above embodiment, the counter 32, 42 and the latch 28
．． 34, etc., but a microcomputer was used in place of these counters 32, etc., and the voice memory 40 and memory control circuit 44 were constructed according to the flowchart A' to T shown in FIG. may be controlled.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional voice sentence repetition sending device, FIG. 2 is a block diagram of a first embodiment of the present invention, and FIG. 3 is a circuit diagram of a memory control circuit. The circuit diagram of the determination circuit 5a and FIG. 5 are block diagrams of a second embodiment in which the present invention is implemented using a microcomputer. 32, 42...Counter 140...Audio memory, 4
4...Memory control circuit% 50...Timer X521
54...O determination circuit. Patent applicant: Toa Tokushu Electric Co., Ltd. Agent: Tetsu Shimizu et al.26 Figure 1

Claims (1)

[Claims] (1) an audio memory in which an audio signal is recorded; a means for transmitting the audio signal υ from the audio memory in response to a start signal; and a means for transmitting a transmission end signal in response to the end of transmission of the audio signal; a timing circuit for generating an output at predetermined time intervals in response to the transmission end signal; and 1) counting the number of times the output is generated and starting when the counted number matches a predetermined first value. a first counting circuit that generates the signal again; and a first counting circuit that counts the number of times the transmission end signal is generated and stops the transmission of the audio signal from the audio memory when the counted value matches a predetermined second value. Stop. and a second counting circuit that generates a signal.