JPS5936968A - Charge transfer device - Google Patents

Abstract

PURPOSE:To enable to always input normal signal charges into a CCD even when the value of DC voltage of the input signal is out of standard by a method wherein the high level value of a signal charge input clock is changed corresponding to the uneven change of the value of DC voltage of the input signal. CONSTITUTION:The charge transfer device is composed of a semiconductor substrate 1 and the group of electrodes 13-22 insulated from this substrate. The signal charge formed in the semiconductor substrate is successively transferred to the longitudinal direction of channels by the multi phase voltage impressed on the electrodes. In the charge transfer device composed in this manner, a switch 54 is connected to the electrode 19, and then this switch is changed over to the upper side when the input signal Vin is at a high level and over to the lower side when it is at a low level. In case of changing the switch 54 over to the upper side, the value of the input clock voltage phi'G changes in proportion to the variation of levels of the input signal Vin by means of a transistor 50 controlled by the input signal Vin. Thereby, abnormal signal charge can be always inputted into the charge transfer device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge transfer device which prevents saturation of the charge of a signal to be transferred regardless of fluctuations in the voltage value of an input DC signal.

As is well known, COD includes a semiconductor substrate and a group of electrodes insulated from the substrate, and by applying multiphase voltages to these electrodes, a signal is accumulated in a potential well formed in the semiconductor substrate. Charge is transferred sequentially along the length of the channel.

Therefore, CCDs are used in many applications in the field of signal processing as delay lines for analog signals.

There are many methods for inputting charge to the COD, but the potential balance method shown in Figures 1 to 6 is widely used because it has relatively little noise (RCA Review VoI, 41
, pp. 29-56, March 1980
).

First, the potential balance method will be explained with reference to FIGS. 1 to 6. In FIG. 1, 1o is a p-type silicon substrate, 12 is an n+ type diffusion layer, 13 to 22 are gate electrodes generally made of aluminum or polycrystalline silicon, and 11 is a silicon oxide layer, which is connected to the substrate 1o and the electrode group. Insulate. Vin is the input signal, voo, VCC is the DC bias voltage, φl, φ
2 is a clock for transferring commercial goods, SP is a pump clock, and φG is a clock for signal charge input, and the clock frequency is sufficiently higher than the signal frequency. FIG. 2 shows the φ1. Amplitude of various clocks such as φ2 + SPIφG 9
Shows phase relationship. FIG. 6 is a diagram illustrating the operation when each clock shown in FIG. 2 is applied to each gate electrode 13-22 shown in FIG. 1.

FIG. 3(a) is a schematic diagram of the COD input section near the substrate surface shown in FIG. Electrodes 13-2
2 shows the potential and charge movement inside the substrate below.

At time to, the internal potential under the n-dosed diffusion layer 12 is as shown by the dashed line in FIG. 3(b). At time tl, when the voltage of the sampling clock SP reaches a high level VspuK, the internal potential under the n-domain diffusion layer 12 becomes as shown by the solid line in FIG. Charges corresponding to the magnitude of the input signal Vin applied to the gate electrode 18 are stored in the potential well. At time t2, the signal '?' applied to the gate electrode 19. ! When the input clock voltage for the input phase reaches VG, as shown in Fig. 3(e),
Gate voltage lji, 15.19.21)'? A signal charge Qs proportional to VG-Vir is applied to the potential well l' formed.
ig is IN'fR. Thereafter, the signal 'fii' and the signal Qs ig are sequentially transferred as shown in FIG. 3(d) by the transfer clocks φl and φ2. The above-mentioned operations are repeated, and the input signal Vi is input into the CCD.
Signal charges Qsig corresponding to n are sequentially input.

FIG. 4 is a diagram showing the relationship between the input signal Vin and the signal charge Qsig. When Vin > Vc, Qsig = 0, and when o≦Vin≦VG, Qsig becomes Vin
changes linearly with respect to In addition, when Vin<VO, Qsig becomes larger than the maximum charge accumulation amount of the potential well in the transfer section of the COD) ax and becomes saturated. As shown in FIG. 4, when performing signal processing using a CCD, the DC voltage value of the input signal is generally used as VDC in order to ensure a dynamic range. However, for example, CO
Considering the case where a television signal is processed using D, the DC voltage value of the television signal constantly changes depending on the inner world of the picture, so as shown by the broken line in Fig. 4,
There is a possibility that the signal charge Qsig will be saturated. In order to prevent saturation of the signal charge Qsig, it is necessary to reduce the amplitude of the input signal, but this poses a problem of deteriorating the S/N ratio of the output signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a charge transfer device which solves the above-mentioned problems of the prior art and can always input a normal signal charge into the CCIJ even if the DC voltage value of the input signal deviates. be.

In order to achieve the above object, in the present invention,
1 (The high level value VG of the load input clock φG is changed in response to the change in level of the DC voltage value of the input signal Vin.

Fig. 5 is a circuit diagram of the main part of one embodiment of the present invention, and 50 in the figure is pn.
p) A transistor, 51 is a resistor, 52 is a variable resistor, 56 is a capacitor, and 54 is a clock φG shown in Fig. 2. When the level is high, it is connected to the upper contact, and when it is low level, it is connected to the lower contact (actually, the drive frequency The other symbols are the first
It is the same as the figure. The capacitor 53 is for removing the influence of the alternating current component of the input signal Vin, and the variable resistor 52 is for removing the influence of the alternating current component of the input signal Vin.
The initial adjustment is made so that the high level value of the output signal φG' of No. 4 becomes Va.

FIG. 6 is a diagram showing the waveform of the actual input clock φcT when the DC voltage value of the input signal Vin changes.
) is a waveform diagram of Vin, (b) is a waveform diagram of φG, and (c) is a waveform diagram of φG'. The function level value of the clock φg+ is the input signal V
When the DC voltage value of in is VDC, it is vG, and when the DC voltage value of input signal Vin becomes small to VI)C++, the base voltage of the transistor 500 decreases, so it becomes a value vG'' smaller than vG. That is, the level value of the clock φG' actually applied to the input gate 19 is proportional to the DC voltage value of the input signal Vin.As can be seen from FIG.
As a result, the clock becomes synchronized with the clock φG.

Figure 7 shows that the DC voltage value of the input signal Vin is VD as described above.
In this figure, the solid line a shows the relationship between the input signal Vin and the signal charge Qsig in the conventional conventional input method shown in FIG.
The dashed line indicates the relationship when the present invention is implemented. In the conventional input method, the signal charge Qsig is saturated (solid line) for an input signal of Vin<Vo, but according to the present invention, the high level value of the clock φG also shifts from VG to VGl'', so that the signal Since the point at which the charge Qsig is saturated also shifts to Vo', the signal charge Qsig no longer saturates by p, as shown by the broken line.

FIG. 8 shows that the DC voltage value of the input signal Vin varies from VDC to VDC.
In this figure, the solid line a shows the relationship between the input signal Vin and the iH charge Qsig in the conventional normal input method shown in FIG. In the conventional input method, for an input signal of V'in>Vc, the signal voltage is saturated (Isig is saturated). According to the above, since the island level value of the clock φG' also shifts from VG to vG' as shown by the broken line, the signal charge Qsig will not be saturated even for an input signal of Vin>Vc.As explained above, the present invention According to the invention, even when the DC voltage value of the input signal fluctuates, a normal (non-saturated) signal charge can always be input into the CCD, and a charge transfer device that operates stably and normally can be obtained. It will be done.

[Brief explanation of drawings]

Figure 1 is a structural diagram of the input section of the CCD, Figure 2 is a diagram of the phase relationship of each clock shown in Figure 1, Figure 3 is an explanatory diagram of the conventional input method, and Figure 4 is the signal charge saturated with the conventional technology. FIG. 5 is a circuit diagram of a main part of an embodiment of the present invention, and FIG.
Figures (a), (b), and (C) are waveform diagrams of input signals, input clocks, and input clocks actually applied to input gates according to the present invention, respectively, in the embodiment of the present invention.
FIG. 7.8 is an explanatory diagram of the effect of the present invention. 10...p-type silicon substrate 12...n-type diffusion layer 13-22...gate electrodes φG, φG'...clock Vin for signal charge input
...Input signal Q s i g... Signal charge 1 Fig. 2 Flash tot1''t273 Fig. 3 M4 Fig. 5 Fig. @6 Kasumi (α) Shima 7 Flash tot 8 Fig.

Claims (1)

[Claims] It includes a charge injection part consisting of an input diffusion layer and a plurality of input gate electrodes, and applies an input signal to one of the input gate electrodes,
Applying an input clock voltage to the other one [7, In the charge transfer device η that sequentially transfers signal charges proportional to the difference between the voltages applied to these two t-poles, the hσ input clock voltage A charge transfer device characterized in that a level value is changed in response to a change in level of a DC voltage threshold value of the input signal.