JPS5936847A - Supervising method of direct memory access device - Google Patents

Abstract

PURPOSE:To write precise data by providing a supervising part and a storing memory for a main memory, and by storing data corresponding to invariable data stored in the main memory in the storing memory to supervise the invariable data and storing data. CONSTITUTION:The main memory address of data to be written is calculted and the ''0'' bit of the invariable data corresponding to the calculated adderss is read in a supervising part 7. Since the sequence of bits in the storing memory 8 is the same as that of data in the main memory 5, the 1st storing data in the storing memory 8 corresponds to the 1st invariable data in the main memory 5. Subsequently, the information of ''0'' bit in the main memory 5 is compared with the correct information in the storing memory 8. The inconsistency of the compared result indicates the destruction of the invariable data in the main memory 5, so that an alarm is sent to prevent incorrect direct memory access.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a monitoring system for a direct memory access device;
Particularly, when writing transmitted data to the main memory of a computer, a monitoring method for a direct memory access device that detects destruction of information in an unchangeable part in the main memory% [Technical background of the invention] Conventional direct memory access device [The operation of the DMA device (hereinafter referred to as the DMA device) is controlled by the remote monitoring and control bag gI'(i
-Explain using an example. In Fig. 1, the conventional remote monitoring and control device tFi transmits various information about the power system, such as generator output values and power flow values of power transmission lines, from an information transmission device 1a (hereinafter referred to as CDT) on the power system side. It is sent to the CDT 1 b on the computer 3 side via the transmission line 2. This C
The transmission data sent to DT 1b is transferred to DMA device 4.
is written into the main memory 5 of the computer 3 by. 9 is a memory path.

FIG. 2 is a diagram showing the structure of data in the main memory, which allows DMA 4. The write operation to the main memory 5 will be explained. Reference numeral 6 in FIG. 2 is a data portion, and the 14-bit data shown in the d portion is the nen data sent from the CDTlb and stored by the Buddha device 4. Similarly, part C of data part 6 is unchanged data and is CDT.
This is not data sent from lb, but data already stored in main memory 5. The O bit, which is constant data, is used to classify whether or not it is necessary to detect a change in the state of data (hereinafter referred to as a state change).

Here, the data necessary to detect a change in condition, such as the circuit breaker on/off
For binary information such as 51, the O bit is 1 (i.e. set, t state)
For data that does not require state change detection, such as numerical information such as the output value of the device, the 0 bit is O (that is, the reset state).Then, the DMA device N? Upon receiving r-data corresponding to the d portion of the data portion 6 from the CDT lb, the CDT 4 reads the C portion of the data in the main memory 5 corresponding to the data, that is, the unchanged data. It then refers to the O bit to determine whether the data is data that requires state change detection, and if it is data that does not require state change detection, the constant data read from main memory 5 and the data received from CDTlb are checked. The data is synthesized into data 6, which is written to the main memory 5 as new data.

Also, if the data is data necessary for detecting a change in condition, the d part of the old data in the main memory 5 corresponding to that data and the CD
Compare the new data received from T 1 b, and if the content has not changed, that t-! ! If it has changed, the reference constant data and CDT are retrieved from the main memory 5, as described above.
After combining the data from lb and putting it into the main memory 5 as new data, it sends an interrupt signal indicating the occurrence of a status change to the i+3 machine 3.

Then, the computer 3 that receives the interrupt signal indicating the occurrence of a state change performs interrupt processing as necessary.

[Problems with background technology]

In the conventional device having the above configuration, if the contents of the unchanged data of the data 6 are destroyed due to a malfunction of the DMA device, the following inconvenience occurs.

That is, the data necessary for detecting a change in condition is CDT la, l
When sent from b to DMA dressing 4, DMA dressing, 4
First, unchangeable data is read from the main memory 5. At this time, the O bit of the read unchanged data is 1, so the main memory 5
Compare the old data (part d) in CDT lb with the new data from CDT lb. If the contents have changed, the unchanged data and new data will be combined and written to the raw memory 5, and an interrupt signal will be sent to the computer 3 to indicate that the state has changed.
During this operation, the O bit of the unchanged data is changed from 1 to 0 by mistake.
If the data changes and is written to the main memory 5, that is, if the unchanged data is destroyed, it will be treated as unnecessary data for state change detection from the next time onwards, so even if a state change occurs (2 Even if the state change occurs, the interrupt signal is not sent to the computer 3. Conversely, when data unnecessary for state change detection is sent and the unchanged data and new data are combined and written in the DMA device 4. , if the O bit of the unchanged data changes from O to 1 and is stored in the main memory 5, from the next time onwards it will be treated as y'-e which requires a change to occur, contrary to the case described above. , every time the sent value changes,
This has the disadvantage that an interrupt signal indicating the occurrence of a status change is sent to the computer 3.

[Purpose of the invention]

The present invention has been devised to solve the above-mentioned drawbacks, and it is an object of the present invention to provide a complete monitoring system for a direct memory access device that can accurately store transmitted data.

[Summary of the invention]

In the present invention, the main memory is provided with a monitoring section and a storage memory, and the storage memory stores data corresponding to unchangeable data in the main memory, and the monitoring section periodically stores data in the main memory. The purpose is to compare the unchanged data in the data stored in the storage memory with the stored data in the storage memory, and to issue an alarm if the data is not equal to 7.

[Embodiments of the Invention] Examples will be described below with reference to the drawings. FIG. 3 is a block diagram of an embodiment of a direct memory access device monitoring system according to the present invention. In Figure 3, the reference numeral 1 in the figure
a, ib, 2, 3, 4, 5, and 9 correspond to the 1191st. Reference numeral 7 denotes a monitoring section, which is connected to the memory path 9. L2 lever monitoring unit 7i1.
A timer that measures the cycle, a data reading section that reads data from the storage memory 8 (described later), a data reading section that reads data from the main memory 5, a data comparison section that compares each of the above data, and a comparison result. It is composed of an alarm unit that sends ff:lf alarms, and a memory that stores the number of data in the memory 5 as well as the start address of the main memory 5.

Reference numeral 8 is a storage memory, in which data is stored using one bit for each data in order to distinguish between necessary data and unnecessary data for the Autumn Test 111, corresponding to the data in the main memory 5. The storage order is the same as the game data in the main memory 5.

Figure 4 is a flowchart for explaining the operation, and the operation in Figure 3 will be explained using this. It should be noted that monitoring of unchanged data is performed from the first data in the main memory 5 to the last data in one execution by the timer.

First step P! In this step, data number i is set to 1, which indicates the first data in main memory 5. In step P2, the address in the main memory 5 of the data corresponding to the data number 1 is calculated and read into the Ovirator X of the unchanged data corresponding to the address. In addition, storage memory 8
Since the bit arrangement in is the same as the data arrangement in the main memory 5, the first stored data in the storage memory 8 and the first unchanged data in the main memory 5 correspond to each other. . Therefore, in step P3, 1 of the storage memory 8 is
Read the pit to y. Next, in step P4, the O-bit information X in the main memory 5 is compared with the correct information y in the storage memory 8.

If X is not equal to y, it means that the permanent data in the main memory 5 yen has been destroyed, so the process moves to step P6, where an alarm signal is sent out, and the process moves to step P. However, if X and y are equal in step P4, the main memory 5
Since the unchanged data in is normal, move to step P.
Check whether the comparison test has been completed for all the data.O When the comparison test has been completed for all the data in the main memory 5, the process moves to step P8, and if it has not finished yet, the data number f:1 is determined in step P7. Increase it and return to Stella fP2. Further, in step P8, the tire measures a preset cycle time, and when the time for the next execution arrives, it sends a signal to start execution, so the operation is placed in a waiting state until the signal is received.

In addition, in this embodiment, the classification code that is necessary and unnecessary for detecting a condition is explained as having a 1-bit configuration and being in the 0 bit of the data, but the classification code can also be a ha configuration of 2 bits or more, or it is limited to 0 bits. It is clear that the invention can be applied to any number of bits.

Of course, even if the cyclic information transmission device t[CDT is not used in the east, the method of the present invention can be applied if data input/output by a DMA device is used.

〔Effect of the invention〕

As explained above, according to the present invention, a storage memory e is provided in the main memory, correct permanent data corresponding to the permanent data in the main memory is saved, and this is periodically compared and examined. Therefore, it is possible to provide a monitoring method for a direct memory access device that can correctly maintain classification codes that are necessary and unnecessary for detecting a change in status.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the case where a conventional direct memory access device is applied to a remote monitoring control device, Fig. 2 is a configuration diagram of data in the main memory, and Fig. 3 is a monitoring diagram of the direct memory access device according to the present invention. FIG. 4, which is a block diagram of one embodiment of the system, is a flowchart for explaining the operation. 1a, lb... cyclic information transmission device, 2...
Transmission path, 3... Computer, 4... Direct memory access device, 5... Main memory,
6°°°r-ta\7... Monitoring department, 8.
...Storage memory, 9...Memory path. Patent applicant Tokyo Shibaura Electric Co., Ltd. Agent Patent attorney Nori Ishii Figure 1 Figure 2 θ Od Figure 3

Claims (1)

[Claims] In the direct memory access method, which writes digital data to the computer's main memory via the direct memory access device, there is a storage memory that saves the correct information of the immutable data stored in the main memory, and a constant memory that is connected to the memory path. A monitoring unit is provided which reads the permanent data in the main memory 5 and the correct information in the storage memory every cycle, and detects corruption of the permanent data in the main memory by comparing and inspecting both data. f! : A monitoring method for direct memory access devices using percentage indicators.