JPS5936385A - Reading circuit of track address - Google Patents

Abstract

PURPOSE:To read quickly and accurately the address information data without clearing a storage element, by referring to the reading address information stored to the storage element in a read mode after counting the reading frequencies of the address information. CONSTITUTION:A clock reproducing circuit 17 and a serial-parallel converting circuit 18 work in response to six same address information signals, etc. of a desired track of a disk 4 passing through a gate circuit 12. Then a track address is formed via a flag detecting circuit 19, an address counter 20, etc. In this case, the counter 20 is controlled by a clock defect detector 23 of a mono-multi which generates an output of a long cycle and therefore forms no erroneous track address which is due to a drop-out, etc. Thus a correct track address is stored in a memory 14. While an address counter 21 counts the number of correct track addresses. The contents of the counter 21 are referred to when the memory 14 is read out by a microprocessor 9. Then a track address is read quickly and accurately out of the memory with no erasion although a drop-out arises.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a stable V. This invention relates to a track address reading circuit that reads address sounds.

Conventional configuration and its problems Figure 1 shows the disc that is the object of the first test.

A certain track (
2) In order to record a group of video signals or the like or to perform reproduction, for example, the track to be recorded is formed in advance in the form of a groove-like track (2) on the disk (1), and When forming the inner track (2), the VC and each inner track (2) are passed from the outer circumference (or inner circumference) of the disk to the inner circumference (or outer circumference) as a phase change of unevenness.
The address information part (3) is formed by the number. In addition, since it is necessary to reliably read the address, as shown in Figure 1, for example, t is 6 pieces of the same address 1, 3 pieces (3-1) (3-2) ( 3-3) Each group is formed into one group 7 and each group is arranged at diagonal positions separated by 180 degrees. It is assumed that the address information is encoded, for example, in BCD (Binary Corchid Decimal) and inkstone-encoded using P)L (Phase Encoding).

Conventionally, when extracting address information from a t'c task, the data in the address information part of the index number sheet taken out with an optical head etc. should be taken out.C.1. The data stored in the # element and then stored in the memory element by the microprocessor is checked and read against the I code, and the majority vote is determined (2) to determine the current track address.At this time, Before storing the data in the address information section in the memory element, or after reading the address information data stored in the storage element VC, it is necessary to clear the information data in address 1 stored in the M+2 memory element.The reason for this. For example, when reading the address information of a new truck, the same 6 address 1N information data of the previous truck are stored in the memory reader, and on top of that, the same 6 address 1N information data of the new truck is read. However, due to reasons such as dropout, only 5 pieces of address information data can be obtained. At that time, when reading the address 1* information of the new track from the memory element, the previous one This is to prevent one address information data of the trunk from being read as address information data of a new truck.

OBJECTS OF THE INVENTION The present invention provides an IC for reading addresses that allows only certain information to be stored in the memory element without overwriting the memory element as described above. The purpose is to provide a circuit.

Structure of the Invention In order to achieve the above object, the present invention provides a disk including a plurality of address information sections corresponding to concentric or spiral tracks, a first means for issuing an address reading command, and a first means for issuing an address reading command from the disk. , the second to take out the @ number on the front part 1
means for detecting a defect in the address information signal from the address information signal extracted by the second means; and an address in the address information section having the defect detected by the third means. The plurality of addresses 1W obtained by the second means except for the data
fourth means for sequentially storing enemy location data of the intelligence unit in a memory element; and reset by an address reading command of the first means;
a fifth means for counting the number of address information parts stored in the Atl writing pupil element by the fourth means; and a fifth means for issuing a city address reading command by the first means; Compatible with deno prayer track 1. a sixth means for detecting that all of the plurality of address 1-ft information sections have been taken out and generating a waste land reading end number r1a; and a tip for detecting the sixth ten-stage land reading end signal; The fifth means reads the number of read address information sections, and then reads the address data of the plurality of address information sections sequentially stored in the memory element of the fourth means. There is also a configuration including a seventh means that reads the number of objects read by the means. .

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Second
In the figure, an optical head (5) extracts an address (IA' signal) from a disk (4), and an amplifier (6) kT'r
It is amplified to the L level, and as shown in Figure 3 (0), while making 3 half-turns of the disk, we obtain 6 of the same enemy territory (g%) per revolution.

(7) in Figure 1 is the rotation start position j mark (hereinafter referred to as V mark and ◇) for the purpose of controlling the phase of rotation of the disk. This y mark (7) is the source of L←・D, etc.) 1 book and uke)
Y: Inset with a V mark detector (8) made of 1M in the container,
Synchronized with one rotation of the disk shown in Figure 3 (b)
Obtain mark number 46.

Now, what is the current track address? ω Trying to take away the secret (temple, microprocessor (after MPtJ tonYbu) (
9) From Arato port (+t) in Figure 3 (c)
A blank-head reading command is output. After the address reading command is output, the address signal extraction pulse generation circuit 0sC, which is composed of a counter or one/zip signal in synchronization with the mark signal, is shown in Figure 3).
River 1B of 2 pulses. This extraction pulse qkoyotsu-L gate circuit 02 extracts only the address (number 4 part) from the output trade name of the amplifier (6).For this reason, the output e of the VJ increase 11 @ 藷 (6) as well as the address 1g. This is because the original data signal is mixed and only the address signal is extracted.

DMA (Direct Mem) consisting of counters
oryACC08θ) The period signal generation circuit OJ is reset by the address reading command of FIG.
The mouthparts are counted twice and the mouthparts are shown in Figure 3 (e). When this signal t, l#H@, MPLI (9
), the address number 1d is the memo IJ.
O, 4) shows the period required for writing. This DMA control signal (hereinafter referred to as DM jg signal)
address bus switching circuit 019 and data bus switching circuit Qe? When each bus is disconnected from the MPU side, it becomes DMAψlK.

On the other hand, the 2W modulated T band signal extracted by the gate circuit (6) is applied to the clock regeneration circuit U to obtain a clock. P in Figure 3 (to)]! The +m11 part of one of the six i-modulated same ground signals is shown in (g), and the clock-regenerated 1d signal φ is shown in (g). In the serial-to-parallel conversion circuit tJ8) constituted by a shift register, the PE-modulated BCLI shown in FIG.

Here, the beginning of the zone signal is shown in (A) of Figure 3 (7j).
Mi1 doesn't have it in the BCD code"?-(1,1,'1
．． 1) Make it a single word coded as I. This is to inform you of the BCII-coated address (the skewer where the 8-bow begins) after the 1P'1 signal.

Serial-to-parallel conversion circuit U barrel to parallel 4 hits each? l change greetings 2Σ
The received address signal is composed of 4 NANDIqj routes)
-Nog detection circuit θ4vc added, 111 described/this number 1
Detect IF@ at the beginning of Tun No. 100 and convert it to Figure 3 (A) V
A C flag signal is obtained. Atre with this flag signal, 7. The counter (E) is started and the clock φ is set to 0/1.
The address signal A is sent to the register. ,
A, , A2 is obtained. This address signal represents one digit of the BCD encoded address signal, and also represents the memory (14J
This is the address signal when storing the address signal. Still, the address counter V (negative) counts the number of clocks φ constituting one address signal, and outputs one address (1g) and one (VC) address as shown in FIG. 3 (3).

+1616 clock φ8 is not generated. The address number counter (2+) is clocked at φ1. The address signal A3. when counting the total number of read addresses and storing the address No. 1d in the memory tJ4). A4. A5 (not shown) is generated. In addition, the number of addresses counter Cυ is shown in Figure 3 (c) VC indicates outboard 1 -
Address 11 created in 1)
No.A. - Based on A5Vc, address data of 4 bits each is obtained directly from the i12 column conversion circuit (g) at a ratio of (2, te 1) rσ) to the 7L14 clocks φ. [not shown] Io-1・1a read 11 is stored in the memory O. The 6 address data on the top of the notebook are stored in the memory (I → (this is stored,
As shown in FIG. 3(E), the DM signal becomes "L".The ILl of D4g causes the address bus switching circuit 9, the cheetack, and the switching circuit U→ to switch between the address bus and the data;
Switch to the MPU (9) side.

On the other hand, after outputting the address reading command via outboard 01, MP[J (9) constantly detects the DMi address via inlet ψ2, confirms that the IJM signal has become 'L1, After that, MPLI (9) is memory θ・0
Outputs the address that selects S and sends it via the data bus.
Read the address data stored in the memory θOV.

Next, the clock loss detector indicated by Hiroya in FIG. 2 will be explained. The clock regeneration circuit (the clock φ from J is added to the clock missing@d-1 device consisting of a one-shot multi-biflator with a time constant whose pulse width is larger than the period of the clock φ. ) Due to reasons such as dropout of the clock φ shown in A33 (G), Figure 3 (E))
(B) V If the clock is missing as shown, the third
A missing detection signal C1 as shown in the figure (Y) Vζ is obtained.

When the clock φ is missing four times as shown in FIG. 3(a), the counter of the address color/ri (e) is reset by the missing detection signal CL. Therefore, the address signal that caused this clock loss activates the address 1/6 counter (21).
! p, 3 rmvcy+z-n(1@riry tsukut
ir, z+;-r tov Not output from the counter (a), A5. A4. A57 Small VC/I-ru1 that is not anovated, I will explain what happens when a clock drop occurs in one of the six address data as the -1 column. At this time, the state 11.1 after reading all the address data from the LD, A of the address number output υ
3. A4. A5 is A3=1, A4-, O, A5
= 1, and the memory (I4) stores the enemy location data read last time (5 locations from the beginning of the memory area; the address data that was washed and 1 keg). Then, MPLI ( 9) ?”, this time the new 7〈Reading Ir
, 1161 The number of addresses 1161 and 1161 is 5, and the number of addresses IAI is outputted via input (a) with a bang.
．． ．． 'l, read from A4= O, A, = 1,
This 11q is MP'' (9:t) By reading only 5 address data from the beginning of the memory area of the memory, accurate bending can be performed.

Next, as shown in FIG. 2, in FIG.
i, 5 "l's" in a row 7)! $ used an impossible small - (, memo the wrong address data') t, 14) v
A small number of poles that do not store C are explained with reference to 4 diagrams 1, 4 t, 1. This is in accordance with No. 31P'1. .

BUD error detector consisting of 5 human-powered NAND circuits (
c) is the 5-bit data from the serial/parallel converter circuit (113).
Detected if there were 5 consecutive digits from 11+ when withdrawing money from the data 2, and 5 consecutive +11s were detected as address data. -1 1194, 'When the enemy territory data is this, the output of the BCD error detector C9 becomes ILI, and this negative pulse No. 713 (not shown) causes the detection 111 signal C1 of the clock missing detector C+. 4) The counter of the address counter is reset at 3. At this time, the clock φ1. shown in Figure 0) is also reset. is not output from Ichino' dress counter (4),
A6. A4. A5 will not be uploaded/
).

The effect of the invention is more than a misfire] V Koyo I [If the address data that has been tainted by tampering with Trotsubout is not stored in the memory, only the address data that is almost certain will be stored in the memory, so the MPU will be able to detect the wrong enemy location from the memory. Since the probability of obtaining data aη is low,
The reading time can be reduced by 11 times.

Furthermore, when the MPU reads the address, the MPU issues a number read command 2, -C, writes it to the memory, stores it, 4fJ111 data 1 is read, and the aPU reads f1. Since it is a construction method, there is no need to erase the old f-location data stored in the memory area when capturing the VC city, so the time it takes to erase the data in the memory can be shortened. .

4 Drawing 1 i1. Q'+n'':r Explanation Fig. 1 shows an example of a disk in which front ground data and a rotation start position mark are formed in advance on the striped guide track. Fig. 2 shows the stratification of the present invention. The circuit block shown in Fig. 1 and Fig. 3 explains the address reading circuit of the present invention shown in Fig. 2 - signal waveform diagrams of various parts of the signboard, and addition to the circuit shown in Fig. 4 ti42. Implementation that brings about effects 43
11' is a circuit block diagram shown in FIG.

(1)...Disc, (2)...Guide track, (
3)...Enemy location information department, (5)...Optical head, (8
)...V mark extraction 8: ÷, (9)...Ma・f Kurogro sesori (M) 'lj), lj('?-・Outboard, QO...Sound order signal removed, pulse generation circuit ,o
2...Gate circuit, (11...DMA period signal generation circuit, prefecture)...Memory, q9...Address bus switching circuit, Middle 9...Data bus switching circuit, Uθ...Clock ( (Multi-generation circuit, a)...Series-parallel two (switching circuit, (A)...address counter, Ql)...Address number counter, (2)...Inhort, wire...Clock missing For detection;
'(-?n / Figure 4

Claims (1)

[Claims] 1. A disk equipped with a plurality of location dissipation units corresponding to VC of a 1HJ circular or spiral track, a first means for issuing an address reading command, and a second means for extracting an address information signal from the disk. , #zth fff 4 from the shoulder/1 hour report signal extracted by the second means.
Except for the third means for detecting a signal defect and the address data of the IT location information section with the defect detected by the previous NL and third means, the plural A fourth means for sequentially storing the address data of the address 17v information part in the storage element VC, and a fourth means for storing the previous n-pi storage element VC, which is set by the Satsuji read command of the first 1st stage of the hII era. It's my turn! After issuing an address reading command using the first means of Ail and the fifth means of calculating the same number of BVs of j in the information section, the second means of R1J reads a plurality of addresses 1R corresponding to a predetermined track V. a sixth means for detecting that all the information has been taken out and generating an address reading end signal; The number of read address information sections obtained by the above means was mulled over, and then the address data of the plurality of landing information sections sequentially stored in the memory element of the fourth means was obtained by the fifth means. The track address reading circuit is provided with a seventh means for reading only the number of welts removed.