JPS593628Y2 - clock pulse oscillator - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to a clock pulse oscillator.

The clock pulse oscillator delivers an output sequence of clock pulses that are locked and synchronized to a certain phase of the binary human pulse train.

In this case, it is locked by random logic levels in RZ signaling at a generally stable bit frequency.

For example, the clock pulses recovered by a clock pulse oscillator are used to reproduce signal waveforms in communication channels or as sampling pulses in sampling circuits.

The Q of a standard clock oscillator with a resonant filter is generally high because the input pulse train with a zero level is transmitted for a long time.

The reduction in the amplitude of the output pulse due to the resonant filter is thereby compensated for.

However, if the resonant filter in the oscillator is made to have a high Q value, there will be the following drawbacks.

That is, the oscillator will not respond faithfully to signals with substantial jitter, and therefore information at the sampler output will be lost.

The primary objective of the present invention is to provide a clock pulse oscillator that delivers clock pulses even though an indeterminate number of resynchronization pulses are missing in the input pulse train, and that resynchronizes with each input pulse. be.

This above objective is distantly related by using an OR gate.

Here, the OR gate has two input terminals and two output terminals, one input terminal receives a synchronizing input pulse train, and the other input terminal is connected to the inverted output terminal of the OR gate. is connected to a delay circuit having a delay time τ.

Note that a sequence of clock pulses is sent out from the other output terminal.

Here, the bit frequency of the synchronous input pulse train is fb,
The delay time τ is defined as τg, which is the signal transfer delay time of the OR gate.

Each single human power pulse resynchronizes the oscillator so that it responds faithfully even to substantially "jittery" signals.

A sequence of clock signals is generated with a phase clocked in relation to input pulses of varying phase.

These clock signals can also therefore be used for reproducing the shape of the input pulses without suppressing any jitter pulses.

Therefore, this clock pulse oscillator can be used, for example, as test equipment.

The present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram of a clock pulse oscillator according to an embodiment of the present invention.

In the figure, an OR gate 10 having a signal transfer delay time τg receives a human pulse 12 and an inverted feedback pulse 14, and outputs an inverted output pulse 16 and a non-inverted output pulse 1.
Generates 8.

The inverted output pulse 16 becomes the inverted feedback pulse 14 via a delay circuit 20.

The receiving terminal of the OR gate 10 that receives this feedback pulse 14 is connected to the voltage source -vl and ground through a resistor 22 and a variable capacitor 24, respectively.

Note that the output clock pulse of this oscillator is a non-inverted output pulse 18.

In this embodiment, a 139,264 Mpph second clock pulse oscillator is used.

The delay circuit 20 is a broadband delay circuit including a coaxial cable with a length of 23 cm and a resistance value of 50Ω, and its delay time τ is.

Here, 几 is the average frequency value of the input pulse 12.

Further, the resistance value of the resistor 22 is 50Ω, and the capacitance value of the variable capacitor 24 is 6 to 18 pF.

2 and 1 to 2 and 3 are waveform diagrams showing states in which the input signal 12 operates at different timings in the circuit of FIG. 1, respectively.

Note that for the sake of simplifying the explanation, τg=Q.

First, in FIGS. 2 and 1, there is a case where the phase of the random input pulse 12 matches the clock pulse (non-inverted output pulse 18) generated by the present oscillator.

In this case, the input pulse 12 has no effect on the operation of the oscillator.

In FIGS. 2 and 2, even if the leading edge of the input pulse 12 is delayed by Δt, the trailing edge of the output pulse 18 temporally coincides with the trailing edge of the pulse 12.

In FIGS. 2 and 3, even if the leading edge of the input pulse 12 is earlier by Δt, the trailing edge of the output pulse 18 temporally coincides with the trailing edge of the pulse 12.

As mentioned above, in all cases the oscillator is resynchronized by one manual pulse.

Therefore, if there is a jitter in the human pulse 12, the oscillator is synchronized accordingly.

For example, some samplers require sampling pulses that match the slightly varying phase of the signal to be sampled/L.

To realize such a sampler, it is sufficient to add one D-type flip-flop to the oscillator according to this paper.

That is, in the circuit including one minute of sound indicated by the dotted line in FIG. 1, a D-type flip-flop pulse 18 is supplied via a delay circuit 26 of an RC filter that observes a delay time τd of 0.7 ns.

The input terminal of this D-type flip-flop 28 is supplied with an input pulse 12 based on RZ data.

If the delay time .tau.g of the OR game 1 is about 1.1 ns, an output signal sampled at the center of the input pulse 12 can be obtained by the delay time 7d and the delay time .tau.g.

The sampling pulse, which in this example is located at the trailing edge of the clock pulse, is generated only once per bit period, and the sampled value is held during the sampling pulse, so that the RZ data is the sampled NRZ data. is converted to

FIG. 3 is a block diagram of an oscillator according to another embodiment of the present invention.

This block diagram shows a delay circuit 21 in which the delay circuit 20 shown in FIG. 1 is divided into a constant delay section 30 and a variable delay section 32, and an OR gate 34 and a DC amplifier 36 are connected in series to the variable delay section 32. are doing.

OR gates 10 and 34 are located in close proximity within the same integrated circuit package.

The variable delay section 3 is controlled by the OR gate 34 and the amplifier 36.
By controlling the delay amount of 2, changes in the delay time due to temperature changes of the OR gate 10 can be compensated for.

To this end, the amplifier 36 must have input/output DC transfer characteristics that compensate for the temperature vs. delay time characteristics of the OR gate 10 and the temperature vs. output voltage characteristics of the OR gate 34.

In the delay circuit 21, the constant delay section 30 is formed by a fixed delay line such as a coaxial cable of a certain length, and the variable delay section 32 is formed by a varactor diode connected to the fixed delay line.

Further, the amplifier 36 is an operational amplifier equipped with a temperature compensation function using a diode.

Such a circuit configuration has a delay time τg of the OR gate 10.
is an integer fraction of the delay time τ of the delay circuit 21, and it is preferable that the delay time τg is a function of temperature.

FIG. 4 is a block diagram of a clock pulse oscillator according to another embodiment of the present invention.

This example is particularly suitable for low bit rates in a wide band from audio synchronous bits up to 50 Mbit/s.

In the figure, the output terminal of the input NOR gate 40, which receives the input pulse 12 at one input terminal, has an inductance L, a coil 42 of (-30 μH), and a capacitance C
1 (=200 pF) and a resistor 46 having a resistance value of R1 (=383 Ω).

The resonant frequency fLC of the resonant circuit is equal to the human power signal frequency (-
2,048 Mbit/sec), and the Q of the circuit, that is, the 2π peak·R−C, is approximately 1.

A clock pulse with a peak frequency is generated from the inverted output terminal of the OR gate 48.

Non-inverting output terminal and OR gate 4 where feedback pulse is generated
0 and the other input terminal, there is an inductance L2 (=
30μH) coil 50, capacitance C2, (=10~40
pF) capacitor 51. Capacitance value C22 (= 180
pF) capacitor 52 and resistance value R2 (-38
A resonant circuit formed by a resistor 54 (3Ω) is connected.

The input pulse 12 is connected to the data input terminal of a D-type flip-flop 60 having a function corresponding to the D-type flip-flop 2B in FIG. is connected to be supplied with the inverted output pulse of the OR gate 48.

This oscillator basically operates in the same way as the oscillator shown in FIG. 1, except that the output clock pulse has a 90° phase lag with respect to the input pulse 12.

The oscillator is advantageously used in sampling circuits, ie the sampling pulse appears at a central point in time depending on the signal pulse to be sampled.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing one embodiment of the present invention;
Figures 2 and 3 are waveform diagrams of various parts to explain Figure 1,
3 and 4 are block diagrams showing another embodiment of the present invention, in which 10.40...OR gates, 20, 21
...It is a delay circuit.

Claims (1)

[Claims for Utility Model Registration] 1. An OR gate having a first input terminal, a second input terminal for receiving an input pulse train of frequency peaks, a non-inverting output terminal for generating a clock pulse train, an inverting output terminal, and the inverting output. A clock pulse oscillator comprising a delay circuit connected between a terminal and the first input terminal, and wherein the delay time of the OR gate is τg, and the delay time τ of the delay circuit is defined as τg. The 20R gate consists of an input OR gate, an output OR gate, and a first phase shift circuit connected between the output terminal of the input OR gate and the input terminal of the output OR gate,
2. The clock pulse oscillator according to claim 1, wherein the delay circuit is replaced by a second phase shift circuit, and the amount of phase shift of both phase shift circuits is 90 degrees at a bit frequency.