JPS61101117A - Sampling clock generating circuit - Google Patents

Abstract

PURPOSE:To fetch an asynchronous reception data with high accuracy by using a variable voltage applied from an external terminal for an operation voltage of inverter circuits connected in cascade receiving a reference clock signal and forming its delay signal, adjusting the delay time and selecting a signal suitable for a digital signal applied asynchronously. CONSTITUTION:A reference clock signal phi0 becomes a clock signal phi1 delayed through one set of inverter circuits. The clock signal phi1 becomes a clock signal phi2 through one set of similar inverter circuits. Further, similarly clock signals phi3-phi8 delayed sequentially by a delay time of one set of the inverter circuits are formed. In changing an operating voltage VS of the inverter circuits, the delay time of the inverter circuits is adjusted to form an optimum sampling clock signal in response to the reception condition.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a sampling clock generation circuit, and can be effectively used, for example, in a sampling clock generation circuit for extracting character information sent in television teletext broadcasting. It is related to technology.

[Background technology]

In television broadcasting, it has been developed to transmit text information using the vertical retrace period. When this character information is received by a receiving device, the received character information is sampled and captured using a clock that is asynchronous with the character information fH formed within the receiving device. As a method of forming this sampling clock, P
Formation using an LL (phase locked loop) circuit is considered. However, the PLL circuit has the disadvantage that it has a large number of components, and since the reference frequency is only sent for a few cycles, it is difficult to obtain a sampling clock that is accurately and stably synchronized with the reference frequency due to its pull-in characteristics. The problem is that it is difficult.

Therefore, the applicant of this application generates a plurality of clock signals delayed by a small amount of time from a clock signal uniquely formed within the receiving device, and selects one optimal clock from among them and uses it as a sampling clock. It was developed. However, with this method, it is difficult to form the above-mentioned optimal clock due to variations in the characteristics of elements constituting the a extension circuit and variations in reception performance of the receiving circuit that receives broadcast waves. In particular, digital signals such as character information received and demodulated in a weak electric field have a small pulse duty, making it difficult to set the sampling clock timing. Regarding the idea of teletext broadcasting, for example, in June 1981,
Published by Asakura Shoten on March 30th, “Collective Circuit Application Handbook J”
See pages 553-557.

C. Object of the Invention An object of the invention is to provide a sampling clock generation circuit that can accurately capture asynchronous received data.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by setting the operating voltage of the cascade-type inverter circuits that receive a reference clock signal and form its delayed signal to be a variable voltage supplied from an external terminal, the delay time i[ffl is calculated and these impark circuits are The most suitable one for the asynchronously supplied digital signal is selected and used from among the clock signals formed by the above.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. In the figure, each circuit surrounded by a dotted line is formed on a semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques. Note that this integrated circuit LSI includes a character extraction circuit for receiving teletext broadcasting. In the same figure,
Of these, only the sampling clock generation circuit for inputting various received signals and digital signals as character information into the launch circuit is shown. As a character extraction circuit other than this sampling clock generation circuit, for example, a circuit similar to the digital predetermined circuit device rHD61921J sold by Hitachi, Ltd. can be used.

The reference clock signal φO is formed by a crystal oscillation circuit (not shown), although it is not particularly limited. Although not particularly limited, this reference clock signal φO can be applied to two
The clock signal φ1 is sequentially delayed by a total of 8 sets of inverter circuits in a cascade configuration.
~φ8. That is, the reference clock signal φ0 is delayed by two inverter circuits in series and is supplied to the multiplexer MPX as a clock signal φ1. This clock signal φ1 is delayed by the two similar series-type inverter circuits described above and is supplied to the multiplexer MPX as a clock signal φ2. Thereafter, clock signals φ3 to φ8 are formed by being delayed by a similar inverter circuit, and are respectively supplied to the multiplexer MPX.

Each of the inverter circuits described above is constituted by a CMO3 (complementary MO3) circuit including an N-channel MO5F'E, T and a P-channel MO3FET, although this is not particularly limited. The power supply terminals of these inverter circuits are separated from the power supply voltage of the integrated circuit and put into operation by being supplied with a variable voltage VS supplied from an independently provided external terminal. In this embodiment, the signal transmission delay time in each inverter circuit is adjusted by making the operating voltage of the inverter circuit variable. That is, the voltage VS is formed by dividing the constant voltage V by a resistor R1 and a variable resistor R2 provided outside the integrated circuit. In addition, in order to reduce the power supply impedance of this variable voltage S to prevent voltage fluctuations from occurring in the voltage vS due to the operation of the inverter circuit,
The resistance values of the resistors R1 and R2 are made relatively small, or an impedance conversion circuit such as an emifukuferroa circuit is provided (not shown).

Next, the operation of this embodiment circuit will be explained with reference to the timing diagram shown in FIG.

The reference clock signal φO is passed through a set of 1° link circuits to form a delayed clock signal φ1. This clock signal φ1 is converted into a clock signal φ2 by passing through a similar set of inverter circuits. Thereafter, black and white signals φ3 to φ8 are formed which are sequentially delayed by the delay time of one set of inverter circuits.

Each of the plurality of clock signals φO to φ8 is delayed by a delay time formed by one set of inverter circuits. In this embodiment, the eight clock signals φl~
Digital signal Din asynchronously supplied from φ8
used for sampling. As mentioned above, the pulse duty of this digital signal Df fluctuates due to the influence of reception conditions and variations in reception characteristics of the reception circuit.On the other hand, the delay time formed by the inverter circuit Since it fluctuates due to variations in characteristics, if the inverter circuit is operated at a constant operating voltage, it is difficult to form a clock signal that is passed through asynchronous digital sampling that fluctuates under various conditions.

In this embodiment, since the operating voltage of the inverter circuit is supplied from an external terminal, the delay time of the inverter circuit can be adjusted by changing the operating voltage VS.

Therefore, it is possible to form an optimal sampling clock signal according to the reception conditions. For example, in FIG. 2, as the sampling signal of the digital signal Din, a signal (Valid) rising at the midpoint of the signal (Valid), such as the clock signal φ4 (or φ5 not shown), is selected by the multiplexer MPX. It is something.

It should be noted that for the purpose of adjusting the delay time, the voltage ■S may be set lower than the power supply voltage Vcc of the internal logic circuit. At this time, the amplitudes of the clock signals .phi.1 to .phi.8 formed by the inverter circuits operated by the relatively low voltage (2) are also reduced by the voltage (2). For this reason, a level conversion circuit is provided if necessary. This level conversion circuit can be realized, for example, by a circuit having a logic threshold voltage close to a voltage of opposite polarity to the operating voltage VS supplied to the inverter circuit. For example, when supplying the circuit ground potential and a predetermined operating voltage VS to an inverter circuit, the clock signals φ1 to ψ8 are pulse signals based on the ground potential, so the level conversion circuit is connected to the circuit ground potential. It suffices to use something with a level close to the electric potential. As a result, each time the operating voltage is made relatively low, the clock signals φ1 to φ8 are
Even if L/H is low], a level-converted clock signal can be formed accordingly. The level conversion circuit may be used in combination with a logic gate or sampling circuit that constitutes the multiplexer MPX.

〔effect〕

(The delay time can be adjusted by operating an inverter circuit that forms a plurality of sequentially delayed clock signals from a reference clock signal using the operating voltage supplied from the external terminal 11.) By adjusting the voltage, it is possible to form a sampling clock signal that corresponds to the reception conditions at the time and variations in reception characteristics of the reception circuit.

(2) It is possible to obtain the effect that asynchronous digital signals can be accurately taken in by a simple circuit such as an inverter circuit that is passed through a semiconductor integrated circuit.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not fixed to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Nor. The variable voltage generation circuit for adjusting the delay time includes an adjustment circuit that compensates for variations in the reception characteristics of the reception circuit and element characteristics of the inverter circuit, and a circuit that performs fine adjustment according to the reception status at the time. It may be configured. Further, the operating voltage of the inverter circuit may be such that a constant power supply voltage is supplied and the voltage on the ground potential side of the circuit is made variable.

[Application field]

The present invention uses input data and a non-open clock signal and can be used as a sampling clock master circuit for capturing the data.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing an example of its operation.

Claims (1)

[Scope of Claims] 1. A cascade-type inverter circuit configured of a semiconductor integrated circuit, which receives a reference clock signal and forms a delayed signal thereof, and which receives sequentially delayed clock signals from the output terminals of these inverter circuits. It is characterized by comprising an output circuit that selectively outputs a sampling clock of a digital signal supplied asynchronously, and a variable voltage generation circuit that supplies an operating voltage to the cascaded inverter circuit through an independent external terminal. sampling clock generation circuit. 2. The sampling clock generation circuit according to claim 1, wherein the asynchronously supplied digital signal is character information sent by television teletext broadcasting.