JPS593548A - 可変長符号の符号変換回路 - Google Patents
可変長符号の符号変換回路Info
- Publication number
- JPS593548A JPS593548A JP11144682A JP11144682A JPS593548A JP S593548 A JPS593548 A JP S593548A JP 11144682 A JP11144682 A JP 11144682A JP 11144682 A JP11144682 A JP 11144682A JP S593548 A JPS593548 A JP S593548A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- bits
- output signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
- H03M7/42—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code using table look-up for the coding or decoding process, e.g. using read-only memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10527—Audio or video recording; Data buffering arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11144682A JPS593548A (ja) | 1982-06-30 | 1982-06-30 | 可変長符号の符号変換回路 |
| CA000431197A CA1211219A (en) | 1982-06-30 | 1983-06-27 | Digital data code conversion circuit for variable- word-length data code |
| EP83303732A EP0098153B1 (en) | 1982-06-30 | 1983-06-28 | Digital data code conversion circuit for variable-word-length data code |
| DE8383303732T DE3380833D1 (en) | 1982-06-30 | 1983-06-28 | Digital data code conversion circuit for variable-word-length data code |
| US06/509,398 US4593267A (en) | 1982-06-30 | 1983-06-30 | Digital data code conversion circuit for variable-word-length data code |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11144682A JPS593548A (ja) | 1982-06-30 | 1982-06-30 | 可変長符号の符号変換回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS593548A true JPS593548A (ja) | 1984-01-10 |
| JPH0117176B2 JPH0117176B2 (enExample) | 1989-03-29 |
Family
ID=14561402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11144682A Granted JPS593548A (ja) | 1982-06-30 | 1982-06-30 | 可変長符号の符号変換回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS593548A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309156A (en) * | 1991-02-13 | 1994-05-03 | Fujitsu Limited | Variable-length code decoding device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051637A (enExample) * | 1973-08-27 | 1975-05-08 | ||
| JPS5319728A (en) * | 1976-08-06 | 1978-02-23 | Fujitsu Ltd | Data treansfer processing system |
-
1982
- 1982-06-30 JP JP11144682A patent/JPS593548A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051637A (enExample) * | 1973-08-27 | 1975-05-08 | ||
| JPS5319728A (en) * | 1976-08-06 | 1978-02-23 | Fujitsu Ltd | Data treansfer processing system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309156A (en) * | 1991-02-13 | 1994-05-03 | Fujitsu Limited | Variable-length code decoding device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0117176B2 (enExample) | 1989-03-29 |
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