JPS5935240A - Emulation device - Google Patents

Abstract

PURPOSE:To emulate varying input data on real-time basis, by equipping the address input part of a storage device with a counter, and combining an address of a CPU and the output of a counter together into an address of the storage device. CONSTITUTION:An RAM1 is stored previously with data using an address generated by combining the high-order digit address 2' and low-order digit address 22. A fixed address from an input fixing circuit 19 is selected 21 as an address 22 when data with only one kind of pattern is stored. When data having many kinds of pattern is stored, the output 20 of the counter 17 is selected 21 as the address 22. The output of the counter 17 is updated successively, many kinds of patterns are written in the RAM1 within the range from the high-order address 2' from the CPU to the maximum counted number of the counter 17. The location where the address of an input part which performs the emulation of reading operation is specified by a mapping circuit 5 is set in a decoder 13, performing the emulation on the real-time basis.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an information processing device system having at least a central processing unit (hereinafter referred to as CPUJ) and an input/output unit that controls input and output of information. (Hereinafter, it will be simply referred to as a "system", and in this case it is assumed that the above requirements are satisfied.

The present invention relates to an emulation device that emulates a CPU ( ), and particularly to an emulation device that can emulate the input/output section of a system in real time.

[Description of prior art]

Conventionally, in this type of device, when the system memory space or input/output section (hereinafter referred to as rIloJ) space is set on the emulation device side, the configuration is as shown in Figure 1. Become.

FIG. 1 shows a circuit of the system side I10 space set in the emulation device when the I10 space is set on the emulation device side, where 1 is a readable and writable storage device (hereinafter referred to as rRAMJ);
2 is a logical address, 3 is a data bus within the emulation device, 4 is a physical address of the CPU on the emulation device side, and 5 is whether the I10 space indicated by physical address 4 is set on the system side or on the emulation device side. 6 is a data bus from the CPU from the system side, 7 is an I10 write signal, 8 is an I10 read signal, 9 is a bidirectional buffer with a high impedance function, 10 is a bidirectional buffer A control signal for controlling the high impedance function of 9 and the RAMI enable function, 11 an OR circuit, 12
becomes active when either I10 write signal 7 or I10 read signal 8 becomes active■1
0 signal.

The operation of this circuit begins with the CP on the emulation device side.
The physical address 4 of U is input to the mapping circuit 5, and from this mapping circuit 5 it is stored in the RAM 1 as the logical address 2.
is input. This logical address and physical address may be the same or different. Next, when the I10 signal 12 becomes active due to the I10 write signal 7 or the I10 read signal 8 becoming active, the mapping circuit 5 sends out a control signal 10 to determine whether or not to put the high impedance sofa 9 into high impedance. Decide whether to enable it. Also, I10 write signal 7 or I1 which is active at this time
The 0 read signal 8 is input to the RAMI, and the I10 read signal 8 is also input to the bidirectional buffer 9 to control the data flow of the bidirectional buffer 9.

In this type of device, when performing normal input/output section emulation, especially input section emulation, the CP
The data input to U is not uniform and has many patterns, and moreover, this data changes continuously. For this reason, when emulating a system in which the input section is specified as the CPU's I10 space using the conventional device shown in Figure 1, after setting this I10 space on the emulation device side, the input will be from this I10 space. Since there is only one type of data pattern, there is a drawback that continuously changing input data cannot be emulated in real time. Also, when writing to the output section, 1
Since only one type of data can be stored in the RAM, it is inconvenient to check after emulation. These shortcomings create a great difficulty in debugging systems with Ilo.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned drawbacks, and its purpose is to
RAM in emulation device specified by address
By continuously reading various patterns of data from the RAM in real time, it is possible to emulate continuously changing input data in real time, and at the same time writing various patterns of data to RAM in real time. An object of the present invention is to provide an emulation device for an information processing device that is capable of inspecting this data after emulation.

[Key points of the invention]

The present invention emulates the central processing section of a system that has at least a central processing section and an input/output section that controls input/output of information by setting the memory or input/output section space of this system on the emulation device side. In an emulation device operated by , the output of a counter in addition to the address of the central processing section is connected to the address input section of a storage device that is provided in the emulation device and is capable of reading and writing and controls the memory or input/output section space. It is characterized by

[Explanation based on examples]

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a block diagram of an apparatus according to an embodiment of the present invention. In the same figure, each code from 1 to 12 indicates the same thing as in FIG. 1. To explain the newly added configuration, 13 is a decoder, 14 is a counter increase signal, 1
5 is a counter decrease signal, 16 is a counter clear signal, 1
7 is a counter, 18 is a selection signal, 19 is a circuit that fixes the input to the selector, 20 is a counter output signal, 21 is a selector, 22 is a lower address to RAM1 (note that 2
' is the upper address of RAMI. ).

Next, the operation of this device will be explained.

First, the RAMI where the I10 space on the system side is set.
First, data is previously stored in the RAMI using an address that is a combination of an upper address 2' and a lower address 22. For storing data having only one type of pattern, the fixed address from the input fixing circuit 19 is selected as the lower address 22, and therefore the address combining the upper address 2' and the lower address 22 is Only one type is available. On the other hand, for storing data having many types of patterns, the counter output 22 from the counter 17 is selected as the lower address 22. Since the outputs of this counter 17 can be updated one by one in sequence, the addresses (outputs of the upper address ten counter 17) can be stored in correspondence with each other for various patterns of data. I can do it. Therefore, RAMI contains [upper address 2]
Various types of data patterns are written in order from [upper address +O] within the range from [upper address 2' to the maximum count number of counter 17].

Next, before starting emulation, the address of the input section (hereinafter referred to as "address A") for which read operation emulation is to be performed is set in the decoder 13. This address A is transferred to the RAMI by the mapping circuit 5.
This is the address specified in . As described above, data patterns to be read within the range from address A (maximum count number of address counter 17) are written in order from address A to the RAMI. Furthermore, the counter 17 is cleared by the counter clear signal 16,
The output of this counter is set to O. It is assumed that emulation is started in this state. Decoder 13
When emulating data at an address other than the address set in , the fixed address 19 is selected as the output of the selector 21 by the selection signal 18, and there is only one type of address that combines the upper address 2° and the lower address 22. becomes. Therefore, at addresses other than the address set in the decoder 13, the circuit of FIG. 2 performs the same operation as the conventional circuit of FIG. 1.

On the other hand, the same address as the address set in the decoder 13 is set as the upper address 2', and the address I10 is set in the decoder 13.
When input simultaneously with the read signal 8, the counter output 20 is selected as the lower address 22 by the selection signal 18. Therefore, the upper address of the RAMI is the address set in the decoder 13, and the lower address is the output of the counter 7 (after the start of emulation, when the first address A continues to be 10, it is O). The contents of the RAMI specified by this address are read into the CPU on the emulation device side. after that,
The output of the counter 7 is incremented by +1 by the counter increment signal 14 outputted from the decoder 13. As a result of this operation, when the emulation device side CPU next performs an I10 read operation at address A, since the output of the counter 17 has been incremented by 1, the contents of address A+1 can be read.

After that, the counter 17 repeats the operation in which its output is further incremented by 1, and the output is sequentially increased.As a result, the CPU is able to continuously read data of various patterns in real time. can.

Next, in the I10 write operation, similarly to the I10 read operation, every time the I10 write operation is performed to the address set in the decoder 13, the counter 17 is decremented by 1 and data is written to the RAMI. This allows the data written after emulation to be sequentially inspected.

In addition, in the I10 read operation, the counter output is increased,
In the I10 write operation, what is decremented is other than emulation. When writing to or reading from RAMI, the counter 17 is automatically incremented by 1 when data is set, and the counter 17 is automatically incremented by 1 when data is checked. -1
This is because the efficiency of the program that controls the 0 emulation device improves.

In the above description, the input/output unit installed in the I10 space has been described, but real-time emulation is similarly possible for the input/output unit installed in the memory space. Further, by specifying the mapping circuit, a part of the conventional configuration shown in FIG. 1 can be replaced with the configuration shown in FIG. 2, thereby improving memory usage efficiency.

Furthermore, by providing multiple decoders and counters, it is possible to emulate multiple input/output units in real time. Debugging becomes more efficient because system emulation can be performed in real time.

〔Effect of the invention〕

As explained above, according to the emulation device of the present invention, real-time emulation 1 is possible even for data having various patterns. It also becomes possible to inspect data of various patterns written in real time after emulation.

[Brief explanation of drawings]

FIG. 1 is a 10 space circuit diagram in a conventional emulation device. FIG. 2 is an I10 spatial circuit diagram in an emulation device according to an embodiment of the present invention. 1...RAM, 2...Logical address line, 2'...
- Upper address, 3... Data bus in the emulation device, 4... Physical address line, 5... Mapping circuit, 6... CPU data bus, 7... I10 write signal, 8... Bow 10 consecutive signals, 9... buffer, 1o... enable signal, 11... OR circuit,
12... OR output signal, 13... Decoder, 14
... Counter increase signal, 15 ... Counter decrease signal, 16 ... Counter clear signal, 17 ... Counter, 18 ... Selection signal line, 19 ... Fixed address, 2
0...Counter output, 2]...Selector, 22...
- Lower address. Z

Claims (1)

[Scope of Claims] +11 By setting the memory space or the human output unit space of an information processing device that is equipped with a storage device that is capable of reading and writing data and has at least a central processing unit and an input/output unit to the storage device. An emulation device that emulates the central processing unit of the information processing device, wherein an address input section of the storage device is provided with a counter, and the address of the storage device is a combination of the address of the central processing unit and the output of the counter. An emulation device characterized in that it is configured as follows.