JPS5935116B2 - sense amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (hereinafter simply referred to as MOST).

), and particularly relates to sense amplifiers used in integrated memories and the like. Although the following explanation will be made for an N-channel MOST, it is essentially the same for a P-channel MOST or other insulated gate field effect transistors.

In integrated memories, one-transistor type memory cells are widely used because the area of the memory cell becomes smaller as the capacity of the memory increases.

In such a one-transistor memory, the charge stored in the storage capacity of the memory cell is transmitted to the bit line via a switching transistor, which is a selection gate, and the minute signal is amplified by a highly sensitive sense amplifier and output signal. Usually, a method is used in which the amplified signal is rewritten into the memory cell at the same time as it is sent out.
Conventionally, the circuit shown in FIG. 1 has been widely used as a circuit for amplifying such minute signals.

That is, the conventional sense amplifier consists of a flip-flop consisting of switching transistors Q1 and Q2 and load transistors Q3 and Q4, the output nodes 1 and 2 of which are respectively connected to the bit lines 3 and 3' of the memory circuit. Both have the same load capacity. Memory cells 4 and 4' for storing signals and reference potential generation circuits 5 and 5' are connected to each bit line, and when the memory cell 4 connected to the bit line 3 is read, the bit line 3'
Conversely, when a memory signal is read out to the bit line 3', the reference voltage generating circuit 5' or 5 generates and supplies a voltage intermediate between high and low binary levels to the bit line 3.
A voltage difference of about 100 mV is created between both bit lines. FIG. 2 shows the voltage waveforms of each clock signal and both bit lines used in the circuit of FIG. 1.

The operation of the circuit shown in FIG. 1 will be described below using the waveforms shown in the same figure. Bit lines 3 and 3' are connected to clock φ3 by time t1.
are precharged to the same constant voltage through transistors Q6 and Q7, respectively.

Next, when, for example, the address line 6 is selected by the address signal and the information in the memory cell 4 is read out, the bit line 3
'', a reference voltage is generated by the reference voltage generating circuit 5', and by time T2, approximately 100 voltage is generated between the bit lines 3 and 3''.
A voltage difference of about mV occurs. At time T2, the clock signal φ
1 is set high and transistor Q5 is slowly turned on, the input signal is amplified by the positive feedback action of cross-coupled transistors Q1 and Q2. As a result, either transistor Q1 or Q2 becomes non-conductive, and the other becomes nearly conductive. Next, at time T3, the clock signal φ2 is set to a high level, and the bit line, which once went low, is set to a high level again by the load transistors Q3 and Q4, whereby the signal on the bit line is further amplified, and the amplification is completed. However, in the conventional sense amplifier shown in Figure 1, DC current always flows through transistor Q3 or Q4 while clock signal φ2 is at a high level, so providing such an amplifier for each bit line would require a large amount of power. , which was a major barrier to the realization of memory. It is an object of the present invention to provide a sense amplifier with low power consumption, and a further object of the invention is to provide a fully dynamic sense amplifier with no DC paths in the circuit.

According to the present invention, the first and second transistors have one drain connected to the other gate, and the gate connected to the second transistor.
a third transistor, also having its gate connected to the second clock line, coupling the first bit line to a first node connected to the drain of the first transistor; a fourth transistor whose gate is connected to the first node and whose gate is connected to the second node and the second bit line, which is connected to the drain of the second transistor; a fifth transistor whose gate is connected to the second node; a sixth transistor whose gate is connected to the second node; a sixth transistor whose drain is connected to the first and second bits; seventh and eighth transistors each having their respective sources connected to ground through a ninth transistor having its gate connected to the fourth clock line and having its gate connected to the third clock line; tenth and first transistors coupling the power supply to the gates of the seventh and eighth transistors, respectively;
and a twelfth transistor whose gate is connected to a first clock line and whose sources of the first and second transistors are grounded.

The sense amplifier according to the present invention satisfactorily achieves the above object in that there is no direct current path in the amplifier circuit, dynamic operation is possible, and power consumption can be reduced.

Hereinafter, in order to better understand the present invention, the present invention will be explained in detail using an example of implementation.

FIG. 3 shows an embodiment of the present invention.

Transistor Q with drain and gate cross-coupled to each other
Output node 1 of the flip-flop constituted by transistor Q1 and Q2 is connected to bit line 3 and the drain of transistor Q7 through transistor Q3, and output node 2 is connected to bit line 3' and transistor Q through transistor Q4.
Connected to the drain of 8. Transistors Q3 and Q4
A clock signal φ2 is connected to the gate of the clock signal φ2. Transistor Q5 has its gate connected to node 1, its source connected to node 2, and its drain connected to gate 4 of transistor Q7. Transistor Q6, whose gate is connected to node 2, has its source connected to node 1, and its drain connected to gate 5 of transistor Q8. Also, transistor Q7
The sources of Q8 and Q8 are commonly connected and connected to the clock signal φ4.
is applied to the gate of transistor Q9. Similarly, the sources of transistors Q1 and Q2 are connected to ground through a transistor Q12, which is commonly connected and has a clock signal φ1 applied to its gate.
Further, the gates of transistors Q7 and Q8 (nodes 4 and 5) are connected to the power supply VDD through transistors QlO and Qll, respectively, to which the clock signal φ3 is applied.
It is connected to the. In addition, in FIG. 3, the clock signal φ3
is applied to the gate and a transistor Ql3 is shown which couples nodes 1 and 2. This 13th transistor is for maintaining nodes 1 and 2 and bit lines 3 and 3'' at the same level. , a precharge clock signal and a clock signal φ2 from the level to be precharged,
It is not necessary if φ3 is sufficiently high. Next, the operation of the circuit shown in FIG. 3 will be explained using the operation waveforms shown in FIG. 4.

Before time t1, bit lines 3 and 3'', nodes 1 and 2, and nodes 4 and 5 are precharged to predetermined potentials, respectively, by clock signal φ3.

It is desirable that this precharge level is at a high potential.
Also, at this time, the clock signal φ2 is at a high level. After the precharge clock signal φ3 becomes low level, when a signal is applied to the address line at time t1, the bit lines 3,
31 and nodes 1 and 2, memory cell information is read out.
When clock signal φ2 is changed from high level to low level at time T2, memory cell information is localized to nodes 1 and 2. To make the following explanation easier to understand, bit line 3 is
Let us temporarily consider the case where the potential of node 1 is higher than the potential of node 2, that is, the potential of node 1 is higher than that of node 2. Then, when the clock signal φ1 is set to high level at time T3 and the flip-flop circuit is activated, the potential of nodes 1 and 2 becomes higher. The potential difference is amplified. When the potential difference between nodes 1 and 2 becomes equal to or higher than the threshold voltage, the potential at node 1 is at a higher level than node 2, so transistor Q5 becomes conductive, and the charge at node 4 is extracted, and the electric charge at node 4 is drawn out.
potential becomes low level. On the other hand, since the potential at node 2 is at a low level, transistor Q6 remains non-conductive, and the potential at node 5 remains at a precharge level (high level). Next, when clock signal φ4 is set to high level at time T4, transistor Q7 becomes non-conductive and transistor Q8 becomes conductive, and the potential of bit line 3'' falls to a low level.On the other hand, the potential of bit line 3 It continues to be held at the precharge potential. As a result, at the end of the amplification operation of this sense amplifier, the potential on the high potential side of the pit line becomes the precharge level, and the potential on the low potential side becomes the ground potential. , it can be seen that in order to increase the amplification factor of the sense amplifier according to the present invention, it is sufficient to increase the precharge potential of the bit line to a high level.

As can be seen from the above description of circuit operation, the present invention provides a fully dynamic low power consumption sense amplifier without a direct current path.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a sense amplifier in a conventional memory circuit, FIG. 2 is an operating waveform diagram of the circuit in FIG. 1, and FIG. 3 is a circuit diagram of a sense amplifier showing a typical embodiment of the present invention. Fourth
The figure is an operational waveform diagram of the circuit of FIG. 3. In the figure, Q is a transistor, C is a capacitor, φ is a clock signal, VDD is a power supply, and 3 and 3' are bit lines.

Claims (1)

[Claims] 1 first and second transistors having one drain connected to the other gate; a first node having the gate connected to a second clock line; and a first node connected to the drain of the first transistor; The third bit line that connects
a fourth transistor, also having its gate connected to a second clock line, and a fourth transistor coupling a second bit line to a second node connected to the drain of said second transistor; a fifth transistor connected to the second node and coupling the second node to the gate of the seventh transistor;
and the gate of the eighth transistor.
seventh and eighth transistors whose drains are connected to the first and second bit lines, respectively, and whose respective sources are grounded via a ninth transistor whose gate is connected to the fourth clock line; , tenth and eleventh transistors having their gates connected to the third clock line and coupling the power supply to the gates of the seventh and eighth transistors, respectively; and a twelfth transistor having a source of the second transistor grounded.