JPS5935113B2 - Buffer memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory control method, and particularly to a buffer memory control method in which a part of the buffer memory is used as local storage.

In a data processing device, part of the data stored in the main memory is set in a high-speed memory called buffer memory, and the buffer memory is accessed instead of accessing the main memory, and the required data is stored. A so-called cache system is used in which if the data is set in the buffer memory, it is used, and if it is not set, it is set in the buffer memory from the main storage and then used.

Recently, advances in technology have made it possible to increase the capacity of the high-speed memory used as the buffer memory, and it has become possible to obtain a memory with a larger capacity than the conventional one.

15- On the other hand, in order to speed up data processing, the central processing unit has a local storage configured with high-speed memory, and stores control information required for channel control and other job processing in this local storage. Setting to storage is done in line 20.

In this case, the local storage can perform normal processing if it has a small capacity compared to the buffer memory, for example, about 256 words, so under the conditions described above where a large capacity buffer memory can be obtained. , the provision of local storage within the buffer 25 memory has no adverse effect on capacity. Therefore, an object of the present invention is to provide a buffer memory control method that makes it possible to provide a local storage area within the buffer memory. In a buffer memory control system having at least two buffer memories and indexing means corresponding to each buffer memory, the address setting means sets 35 the address of the buffer memory, and the upper address of the address is a specific code. an identification means for identifying this, a first constant generating means for generating a first address of the first area of the buffer memory, and a second constant generating means for generating the first address of the second area of the buffer memory. , the above second buffer memory
The area is used as a local storage area, and when the address information set in the address setting means indicates the second area, the upper address thereof is replaced by a constant generated by the first constant generating means. It is characterized by the following.

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation, and FIG. 3 is a partially detailed diagram of FIG. 1.

In the figure, 1 is an address register, 2 is a first tag memory, 3 is a second tag memory, 4 is a first buffer memory,
5 is a second buffer memory, 6 and 7 are comparators, 8 is a buffer memory address generator, 9 is a multiplexer, 1
0 is a main memory, 11 is a decoder, 12 is a first constant generation circuit, 13 is a second constant generation circuit, 14, 15, 16 are AND circuits, 17 is an OR circuit, and 18 is an address register.

Address register 1 is a register in which the address for accessing the main memory 10 is set, and the upper address is set in section 1-0, the middle address is set in section 1-1, and the lower address is set in section 1-0. It is made up of sections 1-2 that are set.

In the first tag memory 2, the upper address in the main storage device 10 of the data set in the first buffer memory 4 is set as data for a directory.
It is accessed using the neutral address and lower address set in address register 1.

The second tag memory 3 is . It has the same structure as the first tag memory 2, and the upper address in the main storage device 10 of the data set in the second buffer memory 5 is also set for a directory. The first buffer memory 4 includes a buffer area in which part of the data stored in the main storage device 10 is set;
It is divided into a local storage area LS, and this local storage area is used to set control information and the like that would be set in a normal local storage. In this case, the main memory 10 is divided into N sets 0, 1, ......N-1, and the first buffer memory 4 is also divided into N sets 0, 1, . Set 0, 1...N-1
Divide into When a data block of a particular set, for example set A, of the main memory 10 is set in the first buffer memory 4, it is written in the same set. A so-called set associative method is adopted. However, since the area LS of the first buffer memory 4, for example, set N-1, is used as a local storage area as described above, the main storage device 1 corresponding to this is used as a local storage area.
When setting the data block of set N-1 of 0 in the first buffer memory 4, set A of the first buffer memory 4 is exceptionally used. Therefore, data block in set A and set N-1 of main storage device 10 are set in set A of first buffer memory 4. The second buffer memory 5 has the same structure as the first buffer memory 4, and is divided into a buffer area where part of the data stored in the main storage device 10 is set, and a local storage area LS. In this local storage area, control information and the like that are set in normal local storage are set. The comparator 6 is for determining whether or not the data to be accessed is set in the first buffer memory 4.
The first tag memory 2 is accessed based on the middle and lower address information k...n set in the address register 1, and the address information and address register read out thereby are accessed. 1 and the upper address set in section 1-0.

If the comparison results match, the accessed data is the first
It can be seen that it is set in buffer memory 4. The comparator 7 performs the same operation as the comparator 6, and uses the address information output as a result of accessing the second tag memory 3 and the upper address set in sections 1-0 of the address register 1. This is a comparison. If the comparison results match, it can be seen that the data to be accessed is set in the second buffer memory 5. The buffer memory address generating section 8 generates address information according to the access destination set in the address register 1, and the details thereof will be described later.

The multiplexer 9 selectively outputs the data output from the first buffer register 4 or the second buffer register 5 according to the output signal from the comparator 6 or 7.

However, the access destination is local storage area L
In the case of S, an LS signal "1" is applied from a control section in the processor (not shown). In this case, the data output from the first buffer memory 4 is output, but when the Err signal indicating that an error exists is [1], the data output from the second buffer memory 5 is output. The decoder 11 outputs "1" to the AND circuit 14 when all [1's] are set in section 1-1 of the address register 1.
1", and outputs "1" to the AND circuit 15 when address information other than all "1" is set.

The first constant generation circuit 12 generates a high-order address [of the start address for set A] when data blocks of set A and set N-1 of the main storage device 10 are set in the first buffer memory 4 and the second buffer memory 5. 0
111".

The second constant generation circuit 13 operates in the local storage area LS of the first buffer memory 4 and the second buffer memory 5.
The upper address [1111] of the first address is generated.

The address register 18 is used to set addresses for the first buffer memory 4 and the second buffer memory 5.

Next, the buffer memory address generating section 8 will be explained in detail based on FIG.

This buffer memory address generation section 8 generates address information that becomes the start address of the area according to the access destination set in the address register 1, and includes a decoder 11, a first constant generation section 12, Second constant generator 13, AND circuits 14, 15, 16, OR circuit 17
It is composed of etc. Now, the first buffer memory 4
When accessing the local storage area LS, the in-area address of the local storage area LS is set in section 1-2 of address register 1,
An LS signal [1] is applied from a control section (not shown).
This turns on the AND circuit 16, so the upper address "1111" of the start address of the local storage area LS, which is generated from the second constant generation circuit 13, is set in the start section 18-0 of the address register 18. be done. At this time, the intra-area address set in the section 1-2 is also set in the lower section 18-1 of the address register 18. Based on the address set in the address register 18 in this way, the required data in the local storage area LS is transferred to the first buffer memory 4.
will be output from. However, the access destination set in address register 1 is
for set N-1, all ``1''s will be set in section 1-1 of address register 1. The decoder 11 detects all [1's] and outputs '1' to the AND circuit 14. At this time, a BS signal "1" is applied from a control section (not shown). As a result, the AND circuit 14 is turned on, and the address information [0111] generated from the first constant generating circuit 12 is set in the leading section 18-0 of the address register 18. Address information [0111
" is the upper address of the first address for set A. At this time, the address information set in section 1-2 is also stored in lower section 1 of address register 18.
8-1, the set A area of the first buffer register 4 or the set N area of the second buffer register 5 will be accessed based on this.
Furthermore, if the access destination set in address register 1 is other than set N-1 of main memory 10, address information other than all [1's] is set in section 1-1 of address register 1. It turns out.

The decoder 11 detects this and outputs "1" to the AND circuit 15. At this time, since the BS signal "1" is output from the control section (not shown), the address information set in section 1-1 of address register 1 is set as is in the first section 18-0 of address register 18. The address information set in section 1-2 is also set as is in lower section 18-1 of address register 18. Therefore, the first buffer memory 4 and the second buffer memory 5 are accessed by the address set in the address register 18.
Next, the operation of the present invention will be explained based on FIG.

first buffer memory 4 and second buffer memory 5
When nothing is set in the first buffer memory 4, data is first set from the main memory 10 in the first buffer memory 4, and then
Data is set in the buffer memory 5 from the main storage device 10. At this time, there is an LRU instruction unit (not shown) that instructs the data set destination, and when the LRU bit is [0], the data set destination is the first buffer memory 4;
When the RU bit is "1", it indicates that it is the second buffer memory 5. Therefore, when data is set in the first buffer memory 4 and second buffer memory 5 as described above, the LRU bits are alternately set to "0" and "0".
1”. There is now a memory access request, and the address register contains the main memory 1 to be accessed.
When an address of 0 is set, first tag memory 2 and second tag memory 3 are accessed based on the addresses set in sections 1-1 and 1-2 of address register 1.

The upper address of the data set at that address is output to comparator 6 or 7, and is compared with the upper address set at section 1-0 of address register 1. For example, if a match signal is generated from the comparator 6, the output read from the first buffer memory 4 based on this signal is outputted via the multiplexer 9. If no match is found, the data sent from the main storage device 10 is set to the buffer memory specified by the LRU bit of the LRU instruction section, and then the other buffer memory is transferred to the main storage device 10. L to set the data from
The RU bit will also be changed. However, when writing control data, etc., in the local storage area LS, the address within the area of the local storage area LS is set in sections 1-2 of address register 1, and at the same time the LS signal is set to "1". do.

As a result, "11" is generated from the second constant generating circuit 13.
1r is set in the first section 18-0 of the address register 18 via the AND circuit 16 and the OR circuit 17, and at the same time, the address in the local storage area set in the section 12 of the address register 1 is also set in the lower section 18.
-1. and the first indicated by this
For example, control data for the local storage area set conveying the addresses of the buffer memory 4 and the second buffer memory 5 will be set. In this way, the same data is set in the local storage areas LS of the first buffer memory 4 and the second buffer memory 5. When reading this local storage area LS, the local storage area address is set in sections 1-2 of the address register 1, and the LS signal is set to "1".

As a result, as mentioned above, the second
"1111" is set from the constant generating circuit 13 in the first section 18-0 of the address register 18, and the in-area address is set in the lower section 18-1. As a result, the first buffer memory 4 and the second buffer memory 5 are read simultaneously. However, the L-S signal "
1'' is applied, this multiplexer 9 outputs the data read from the first buffer memory 4 as described above. However, if a parity error or the like is detected in this output data, an Er
The r signal becomes "1", and the data in the local storage area read from the second buffer memory 5 is now output instead of the data read from the first buffer memory 4. In addition, if the access destination set in address register 1 indicates the local storage area LS, the address register 1's section 1-
Address information set to 1 becomes all [1].

This is decoded by the decoder 11 and "1" is output to the AND circuit 14. At this time, the BS signal becomes "1" and "0111" is set in the first section 18-0 of the address register 18 from the first constant generating section 12. Since the address set in the section 1-2 of the address register 1 is set in the lower section 18-1, the set A area of the first buffer memory 4 or the set N area of the second buffer memory 5 is read out. become. At this time, the first tag memory 2 and the second tag memory 3 are read by the addresses of sections 1-1 and 1-2 set in the address register 1,
Comparators 6 and 7 compare the upper address O. It is determined from the outputs of the comparators 6 and 7 whether or not the desired data is set in sets A and N. If the desired data is set, it can be obtained from the multiplexer 9. As described above, according to the present invention, it becomes possible to use a partial area of the first buffer memory and the second buffer memory as local storage.

Moreover, since the same data is set in each of these local storage areas, one can be used for backing up the other. For example, if there is an error in the data read from the first buffer memory, correct data can be read from the second buffer memory. According to the invention, therefore, local. By using a portion of the buffer memory for storage, not only can you save memory for local storage, but you can also use one buffer memory for backup, improving data reliability. I will do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation, and FIG. 3 is a partially detailed diagram of FIG. 1. In the figure, 1 is an address register, 2 is a first tag memory, 3 is a second tag memory, 4 is a first buffer memory,
5 is a second buffer memory, 6 and 7 are comparators, 8 is a buffer memory, address generator, 9 is a multiplexer, 1
0 is a main memory, 11 is a decoder, 12 is a first constant generation circuit, 13 is a second constant generation circuit, 14, 15, and 16 are AND circuits, 17 is an OR circuit, and 18 is an address register.

Claims (1)

[Claims] 1. In a buffer memory control system having at least two buffer memories and indexing means corresponding to each buffer memory, an address setting means for setting an address of the buffer memory, and an address setting means for setting an address of the buffer memory, and an upper address of the address when the upper address of the address is a specific code. An identification means for identifying this, a first constant generation means for generating the start address of the first area of the buffer memory, and a second constant generation means for generating the start address of the second area of the buffer memory are provided. The second area is used as a local storage area, and when the address information set in the address setting means indicates the second area, a constant generated by the first constant generating means is used to specify the upper address thereof. A buffer memory control method characterized by replacing the memory.