JPS5934777A - Picture signal processor - Google Patents

Abstract

PURPOSE:To record a recording signal with high quality at a high frequency band, by providing an image pickup section having plural picture elements arranged in matrix, and a picture element memory recording digitally each picture element outputted from the image pickup section so as to unify said section and a recording section. CONSTITUTION:A discrete output of a solid-state image pickup element 12 scanned at a driver 10 is amplified at a preamplifier 14, sampled and held into a continuous signal, and inputted to an A/D converter 16. The solid-state image pickup element 12 has a single board inter-line CCD having picture elements arranged in a matrix, e.g., attended with R, G, B, mosaic filters. An A/D converter 16 converts an output of the preamplifier 14 into a digital signal in 8-bit per each picture element and writes it into a picture element memory 18. A data of 2O bit among each picture element data is stored regularly in a memory 18-1 in the order of picture element. The data corresponding to 2<7>-bit is stored similarly in a memory 18-8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing device suitable for recording images, particularly still images.

Conventionally, not only moving images but also still images with no temporal element have been recorded electronically. For example, analog NT for l frames output from a video camera such as a VTR.
After the SC signal is converted, it is written to the frame memory. After the signal read from the frame memory is converted, it is supplied to a monitor CRT or printer, and an image is reproduced. Here, still images require higher resolution than moving images, but the current NTSC system does not meet the resolution requirements for still images. On the other hand, a high-definition television system in which the number of horizontal scanning lines is set at 1125, approximately twice that of the current NTSC system, is being considered, mainly by NHK. If this high-definition television system is used, satisfactory results can also be obtained in recording still images. However, in this high-definition television system, the frequency band of the video signal is several times higher than that of the current NTSC system, so it is impossible to apply it directly to conventional equipment. In particular, the sampling frequency of the ~Φ converter and the capacity of the frame memory are problematic. Generally, the sampling frequency of the converter should be set to 3-4 times the color subcarrier frequency (3,53 MFIz). Therefore, in the current NTSC system, the sampling frequency is 14.32MHz (3,58MI (z
x 4).

Further, if 8 bits are required for one pixel, it becomes a frame. In contrast, in high-definition television systems,
The color subcarrier frequency is 24.3 MJ (z), so the sampling frequency is 97.21 ViHz (24,3 M[(
zX4).

The frame memory capacity is approximately 26Mbit (8 x 97.2
×35). Circuits that generate such high-frequency clock signals are not suitable for portable equipment due to price, volume, and power consumption. This portability is very important in such devices. Furthermore, a large frame memory is required, making it impossible to directly apply this high-definition television system to conventional equipment.

This invention was made to deal with the above-mentioned circumstances,
The object is to provide a portable image signal processing device that records still images at high resolution.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image signal processing apparatus according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of the first embodiment. CCD as an image sensor for the driver 10
12 are scanned. The scanning speed may be the usual 30 frames/second.

The CCD 12 has imaging pixels arranged in a two-dimensional (IJ) wax-like manner. In addition to CCD, B is used as an image sensor.
BD+MO8FET may also be used. Further, the signal transfer format of the CCD 12, which may be a small-sized image pickup tube, may be a frame transfer method or an interline transfer method. An analog image signal output from the CCD 12 is supplied to an A/D converter 16 via a preamplifier 14. Preamplifier 14 performs amplification and sample/hold. ~The raw converter 16 converts the image signal into 8 pixels for each pixel.
Convert to a BLT digital signal. The output signal of the φ converter 16 is also written to the pixel memory 18 for each pixel. Therefore, even if the number of pixels is 1000x1000 elements, each pixel in the pixel memory 18 may have 8 Mbit. In addition, the sampling frequency of the A/D converter 16 and the 6-inclusive clock frequency of the pixel memory 18 can be set equal to the black and white frequencies of the CCD 12, so approximately 30 to 11 (
z (1000X'1000X30) is sufficient. These conditions are achieved with a sufficiently small size, light stitching, and low power consumption.

If the image signal output from the CCD 12 is performed separately for each of the primary colors R, G, and H, the sampling frequency of the ψ converter 16 may be further reduced to a fraction thereof. The pixel memory 18 is composed of a semiconductor memory element, the details of which are shown in FIG. Here, suppose that the output signal of the converter 16 is an 8-bit serial signal, and the multi-breather 44 converts 1 to B b
It is distributed for each it-th component. The pixel memory 18 consists of eight memories each having a capacity of 1 Mbit, and each day is written into each memory component by component. After the output signals of each memory are multiplexed by the multiplexer 46, the D/
A converter 20 is supplied. Here, A/D transformer 16
If the output signal is an 81t parallel signal, the multi-brephuser 44 is unnecessary. The pixel memory 18 stores pixel positions, luminance, and signals having two color components.1. a.

The signal read out from the pixel memory 18 is supplied to the process amplifier 22 via the converter 20. By adjusting this readout frequency, fixed pattern noise of the image sensor can be suppressed and vertical smear can be reduced. Driver 10, CCD 12, preamplifier 14
．． A7T) Converter 16, pixel memory 1B, D/A
The timing of conversion 520 is performed by system controller 24. When recording a captured image in the pixel memory 18, the system controller 24 stores the driver 10, l
The VD converter 161 supplies relatively high-speed reference signals, timing signals, and control signals to the pixel memory 18, and when reading the recorded pixels in the pixel memory 18, the pixel memo IJ1
8. The process amplifier 22, which supplies the D/A converter 20 with a relatively low-speed reference clock, timing signal, and control signal, converts the output signal of the pixel memory 18 into a high-definition television set.
The video signal is converted into a composite video signal compliant with the /Yon system, and is supplied to the recording circuit 26. In this embodiment, the frame image recorded in the pixel memory 18 is re-recorded in yet another large capacity memory, here a magnetic recording means. The recording circuit 26 frequency-modulates and amplifies the composite video signal and supplies it to the magnetic head 28 . The magnetic field 28 causes a magnetic recording medium 30 such as a tape or a disk to generate magnetic information according to the video signal.

This recording may be analog or digital. Since the readout frequency from the image memory 18 can be set lower than the clock frequency of the image sensor 12, the capacity/bit number ratio, power consumption, and operating speed of the converter 20 and the subsequent converters are limited.

Due to cost etc., magnetic chips, magnetic disks, optical-magnetic disks, CMOS memory, bubble memory.

Select from EEPROM, MONOS memory, etc.

A changeover switch 32 is provided between the recording circuit 26 and the magnetic head 28.
28 is used for both recording/reproduction and magnetic field. That is, the first contact of the changeover switch 32 is connected to the recording circuit 26 , the movable contact to the magnetic head 28 , and the second contact to the reproduction circuit 34 . The output signal of the reproduction circuit 34 is supplied to a frame memory 38 via a converter 36. The output signal of the frame memory 38 is connected to an interface 42 via a converter 40.
supplied to

The circuit portions after the reproduction circuit 34 do not necessarily need to be built into the portable device main body, and may be provided separately. The output signal of the interface 42 is transmitted to a monitor CRT (not shown).
, supplied to printers, etc. The read speed of the frame memory 38 is determined to match the operating speed of these external devices. This confirms the recorded image.

In the first embodiment, if the frequency characteristics of the re-recording system are relatively close to the frequency characteristics of the main system system such as the pixel memory 18, it is possible to share some circuits as shown by the broken line in FIG. That is, the output signal of the regeneration circuit 34 and the converter 16
The pixel memo IJJsK is supplied via the pixel memory IJJsK. This signal is supplied to the interface 42 via the D/A converter 2o. In this way, the converter 36. that you want to surround with a broken line.
The frame memory, 9s, and D/A converter 40 become unnecessary. However, in this case, since the pixel memory 18 operates as the frame memory 38, it is necessary to increase its capacity.

As explained above, according to this embodiment, the output image signal of the image sensor is subjected to color processing and filtering.

The data is converted and written into the memory element as is without being subjected to any programming or the like. Therefore, it is an ugly converter.

The operating frequency of the memory element can be lowered, the capacity of the memory element can be reduced, and an image signal processing apparatus that does not lose portability even when the resolution is increased is realized.

Hereinafter, in describing other embodiments of the present invention, parts corresponding to those in the first embodiment will be designated by the same reference numerals and their explanation will be omitted. The second embodiment shown in FIG. 3 differs from the first embodiment in the connection position of the cross section 7'22. That is, the process amplifier 22 is connected not between the D/A converter 20 and the recording circuit 26 but between the D/A converter 40 and the interface 42. After the output signal of the pixel memory 18 is 1)/A converted, it is converted to -b) memory 3 without passing through the process amplifier 22.
8. The process amplifier 22 is connected to the process amplifier 22 before the signal successively outputted from the frame generator is supplied to the interface 42.
is converted into a composite video signal or component video signal. According to the second embodiment, since the output signal of the CCD 72 remains unchanged up to the stage before the gross processing unit 22, the capacity of the frame memory 38 can be made equal to that of the pixel memory 18. Even in this case, if you connect as shown by the broken line, the ψ converter 36, frame memory 38, D/
The A converter 40 becomes unnecessary.

FIG. 4 shows a third embodiment of the invention. Here, CC
The output signal of D I 2 is obtained for each of the three primary color components of R7°G and H by the action of the R, G, and B spectral filters.

Therefore, a preamplifier 14° ψ converter 16, a pixel memory 18, and a D/A converter 20 are provided for each primary color component. The output signal of the preamplifier for the G component is supplied to the CRT 52 via the gross amplifier 50. CB, T5
2 is attached to the finder section of the main body of the device, for example.
A monochrome CRT of approximately 1 nch, called an electronic viewfinder, may be used. That is, Grosses Ang 50
generates a black and white video signal.

Therefore, real-time display of recorded images is possible.

In this example, Grosse Anne 7',? 2 is the luminance signal Y
A component video signal consisting of a wideband color difference signal Cw and a narrowband color difference signal CN is generated, and a magnetic field 28 is provided for each component.

A high frequency synchronous circuit 54 is a driver 10 and a preamplifier 1.
4, the ψ controller 56 and the memory controller 5-8 are controlled, and the low frequency synchronous circuit 60 controls the memory controller 511, the D/A controller 62, and the gross
Control 2. The memory controller 58 is the pixel memory 1
When the pixel memory 18 is in the 9M included mode, it is controlled by the synchronizing circuit 54, and when the pixel memory 18 is in the read mode, it is controlled by the synchronizing circuit 60. The circuit portions after the reproduction circuit 34 are omitted from illustration.

An example of the CCD 12 in this embodiment will be explained. FIG. 5 shows a line-sequential type CCD. Imaging pixels arranged in a two-dimensional matrix - color strip filter RQ
G. , B are repeatedly arranged for each horizontal scanning section. The image output for each horizontal inspection section is determined by the selector 66 for each color.
Supplied at 68.70. Alternatively, the selector 66,
R, G without using 68°70. , B may be serially read out and divided in a time division manner. Also, CCD
If the operation of 12 is high speed, selector 66°68.70
An analog shift renostar or the like of IH level may be provided between the A/D converter 16 and the preamplifier 14 to slow down the circuit operation after the A/D converter 16. Also, although not shown, the frame transformer 77
A system CCD may also be used.

The pixel memory 8 of the third embodiment will be explained. Here, the number of pixels is 1125 (V)
Assume that a 13-bit dinotal signal is recorded per pixel. Since the output signal of CCD 12 is processed for each primary color of R, G, and B, the pixel memory capacity for each color is approximately 4 Mbl.
t (1125X1398X, X8bit). 8
If a bit signal is recorded bit by bit for each color as shown in FIG. 2, it is sufficient to provide a 512 kbit memory element for each bit. Note that if the CCD 12 is operating at 30 frames/second, the output of the CCD 12 will be 1. In the case of 7 reals as in the second embodiment, the clock frequency is about 45 MHz (1125 x 1398 x 30), but in the third embodiment it can be lowered to 1.

The fourth embodiment shown in FIG. 6 differs from the third embodiment in the re-recording method. In this embodiment, the output signal of one converter 2θ is directly supplied to the recording circuit 26 without going through the gross angle. Recording circuit 26d Frequency modulates the image signal and outputs R, G
, H are supplied to the magnetic field 28 in a component manner. Since this method does not generate a Grosses Ang KJ rainbow luminance signal, the readout speed of the pixel memory 8 is controlled by the recording circuit 2.
If the recording speed is set to be the same as No. 6, it is also suitable for recording high-quality moving images. Note that in the case of video recording, the output signal of the preamplifier 14 may be directly connected to the recording circuit 26.

The fifth embodiment shown in FIG. 7 is a mixture of the R, G, B component method and the composite method. That is, pixel memory 1
The signal read out from the pixel memory 18 is processed using the R, G, B component system until it is written to the pixel memory 18, and the signal is multiplexed by the multi-blephr 72, and when it is re-recorded on the magnetic recording medium SOK, a composite video signal is recorded. Ru.

In the above-mentioned embodiment, a single-chip COD was used as the image sensor; however, the present invention is not limited to this, and a multi-chip CC with two or three sheets may be used.
D may also be used. In this case, a Griang is also provided for each version, and the output of the Griang is multiplexed by a multi-blephr.

As described above, according to the present invention, there is provided an image signal processing device that is compact, lightweight, and capable of recording high-quality still images with low power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of an image signal processing device according to the present invention, FIG. 2 is a diagram showing the configuration of a memory used therein, FIG. 3 is a circuit diagram of the second embodiment, and FIG. FIG. 5 is a diagram showing the configuration of the image sensor of the third embodiment, and FIGS. 6-7 are circuit diagrams of the fourth and fifth embodiments. 12...CCD, 16...A/D converter, 18...
- Pixel memory, 20... converter, 22... gross conversion, 26... recording circuit, 28... magnetism, de, 30... magnetic recording medium. Procedural amendment It? ! +t+ 4 seconds 8.1B1゜11j゛Mr. Kazuo Wakasugi, Director-General of the Permanent Office■,・Former/
No. 7 Indication Patent Application No. 144561/1988 2 Title of Invention Image Signal Recording Device, 'L'fIili, l: Relationship with Nasuh Incident
Patent applicant Tsu9, (o: +7) Olympus Optical-1 Kuri Co., Ltd. r (
-4, Agent 5, Voluntary amendment 7, Self-answer of amendment (3) Aim Diagram 1 to Diagram 7 are corrected as per separate review,
Add attached figures 8 to 17. Akira MJU4F 1 Name of the invention Image signal recording device 2, Claims (1) An imaging means having a plurality of pixels arranged in a matrix, and an analog bi-system signal for each pixel output from the imaging means. An image signal recording device comprising an A/D conversion means for converting into a pixel signal, and a pixel memory means for recording a digital pixel number output from the A/1) conversion means for each pixel. (2) The virtual image means outputs a plurality of color component signals each having a different color component, and the conversion means and the pixel memory means process a signal for each of the tomoe and r?- component signals. An image number recording device according to claim 1. (3) A patent characterized in that the imaging means sequentially outputs different color component signals to each horizontal scanning line center. Image 1g recording device according to claim 2. (4) Image 1g according to claim 2, wherein the virtual image means simultaneously outputs component signals of each color in parallel to produce a zero value. (5) The separate imaging means consists of a frame transfer type COD that sequentially outputs a different Tomoe component signal for each pixel, and a selector that divides the serial output of the CCD into component signals of each color for each pixel. The image signal recording device according to claim 2, characterized by the symbol f! (7) The number of pixels of the imaging means is approximately 1125 in the vertical direction.
15J and 1g recording device according to claim 1, characterized in that the X horizontal direction is 1365. (8) The capacity of the pixel memory means is MXN bits (here, M is the number of pixels of the image means, and N is A/1).
A special F1f whose special feature is the number of bits of the conversion means.
The image signal recording device according to item 1 of the FTS requirements. (The image signal recording device according to claim 1, characterized in that a re-recording means having a larger capacity than the 97-pixel memory means is connected to the output of the pixel memory means.) Image recording device No. 1 according to item 9 of scope 6 of the clock, characterized in that both the imaging means and the frequency band are low, and the signal is read out from the pixel memory means at a speed slower than the writing speed. 1. The image signal recording device according to claim 10, wherein the re-recording means is a solid-state memory that operates in the frequency band of the NTSCTV system or a memory that involves relative movement. , Detailed Description of the Invention The present invention relates to an image signal recording device suitable for recording an image signal representing image No. 1g, particularly a still image. An image No. 15 recording device that records the image as a single aperture signal has been put into practical use.Currently, the specifications of the image signal are close to the current television system.Therefore, the recorded image signal The still images obtained as a result of playing back are inferior to photographs taken with conventional cameras in terms of resolution, color tone, etc.Therefore, in image signal recording devices such as this, which target still images, teeth,
It is desired to improve the quality of images. By the way, the picture is 1M! Generally speaking, the biggest problem in improving the quality of images is that the frequency band of the 100th image being handled shifts to a higher frequency band. For example, the high-definition television system proposed by NHK has the following specifications. The numbers within 0 are the specifications of the current NTSC television system. Luminance signal γ) band 201ViHz (4,5
MHz) Color difference signal Wideband color difference signal (Cw) 7 MHz (1,5M
Hz) Narrowband color difference signal (CN) 5.5MHz (
0.5MHz) Color subcarrier frequency 24.3MHz
(3,58MHz) Horizontal scanning frequency 33.7
5 KHz (15,74 KHz) frames per second
30 frames, (same) number of horizontal scanning lines
1125 lines (i.e., in high-definition television system, the frequency band used is 20-30 MH)
However, it requires several times the bandwidth compared to the current NTSC system. FIG. 1 shows a conventional example of a single-picture recording and reproducing apparatus for this high-definition television system. 3-! The R, G, and B component signals from the F-type high-definition TV right camera 10 are supplied to the matrix circuit 112, and a brightness signal Y, a wideband color difference signal C1, and a narrowband color difference signal CN are obtained. A synchronization signal is added to the luminance signal Y by the synchronization addition circuit 114, and then the luminance signal Y is supplied to the magnetic head 220 of the first channel via the frequency modulator 116 and the recording amplifier 118. The Cw and CN signals are converted into one signal via the line sequential conversion circuit 122f and supplied to the magnetic head 128 of the second channel via the frequency modulator 124 and the recording amplifier 126. The carrier frequency of frequency modulation D116°124 is 34
．． 5 MHz. Magnetic Rad 120, 12& records the signal on Magnetic Rad 1130 (0.5 m diameter). The magnetic notebook 130 is rotated by a motor 132 (
60rps), and is moving at 84rIV/s relative to the 4i air head 12θ, 128. The output luminance signal of the four-channel addition circuit 114 is supplied to a sync separation circuit 134, where a sync signal is separated. The clock 4Jf of 601 (z) is generated from the clock generator 136 by the output of the synchronous separation circuit 134, and this is supplied to the motor 7.92 via the drive amplifier iagy. between the recording amplifiers 118, 126 and the magnetic helenoid L'12θ.
42 is provided, and a company air head 12o is provided. No. 18 from No. 128 is supplied to the reproduction side. That is,
The first channel's student, No. 1g, is from LJJ Housu Switch 140 to playback amplifier 144, equalizer 146, FM
The demodulator 148 outputs a luminance signal Y. The 41+ raw signal of the second channel is transmitted from the switching switch 142 to the reproduction amplifier 1501F'M modulator 152, the winning sequential inverse transformation circuit 154, the wideband color difference signal CW, and the narrowband difference signal CN. It is said that Luminance signal Y, II: band color -1
The 9th picture number (:, the color difference I M number CN is supplied to the matrix circuit/5 ti IL, It, G, n component 7J?- component signal and δ is supplied to the Akane quality CRT monitor 158,
A color still image of 1,125 trees with horizontal movement is printed. In addition, for the reproduction thread (monitor system) during recording, the output of the frequency modulators 116 and 124 is the same as the FM demodulator 14R, as shown by the broken line.
, 152. Such high-definition image 6 self-recording (external equipment is high frequency (
Record No. 1E in the if' area using a large magnetic / (
(), the equipment has become larger and is being developed as a stationary type equipment. Therefore, this device &its cannot be used in place of a conventional camera. The image recording and reproducing device for oJ floor striking is required to be small, lightweight, low power (aJ' used in K pond), and low cost. The 6C recording and reproducing apparatus shown in FIG. Since the information is recorded on a magnetic/-t), it cannot be depicted as a portable device. Figure 2 shows a system for recording one frame of video 1d output from a TV camera in a frame memory in the current NTSC system. Analog color component signal W obtained as a result of photoelectric conversion
(white), Ye (yellow), Cy (noan),
G (green) is supplied to a matrix circuit 164 via a Noriamp 162. The IhG and H color component numbers obtained by the matrix circuit 164 are 1^.
The signal is supplied to the noise IC 170 via the constant pattern noise suppression ICj66 and the low and e-s filters 16B. The output of the fixed pattern noise 4+111E IC 166 is also supplied to the vertical smear reduction circuit 172. The output of process IC 170 is supplied to encoder ICl 74,
A synchronization signal from the synchronization IC 176 is added, and NTSC video 11M! It is considered a signal. The NTSC video signal output from the encoder ICJ74 is digitally written into the frame memory 182 via the buffer 178 and the converter 180. The embedded frame image is recognized by the electronic bea finder 18''4 connected to the output end of the buffer 17B. In the N'rSC method, the frequency band of the video signal is O~4,5.
MHz (for commercial use) or 0 to 2 MHz (for consumer use). When A/N converting a video signal, the sampling frequency is set to 3 to 4 times the color subcarrier frequency 'ac. In the NTSC system, FLLC is 3.58MH8, so if it is multiplied by 4, the sampling frequency is 3.58.
X 4 = 14.32 MHz. Furthermore, when one sample data is converted into 8 bits, the capacity of the frame memory for erasing one frame's ll7iI image kH becomes 8 x 14.32 x 1/30# 3.8M bits. Here, the 1g band of the A/D converter 180 is 0.
~10 MHz, as shown in Figure 3, 14
．． 32 MHz is the Nyquist frequency, and the video signal near this frequency and the sampling signal of the A/l) converter 180 cause a beat, that is, aliasing. Therefore, the frequency band of the video signal is limited by the low-pass filter 168 as shown by the broken line in FIG. Note that in such a 7-stem system, the solid-state image sensor 1
The signal for each pixel of 60 pixels is one analog NTS
While being converted to a C signal, it is converted to A10 and written to frame memo 1) zsz. Therefore, A, '1) Slight deviation in sampling frequency during conversion, phase deviation of analog circuit, etc.
Information about each pixel is not necessarily recorded as is in the frame memory for each pixel. When the recording system shown in Fig. 2 is applied to the above-mentioned one-island quality image, the sampling frequency of the A/b transformer is 24.3.
X 4 = 97.2 MHz, which is #-2 in m
Pure Body (In the branch technique, 1lIII case d, ■, it cannot be applied to the mouth-carrying device in terms of consumption' formation power.Furthermore, the W and gift of frame memory are also 8 x 97.2 x l/30 = 26
M-bit also has 9IjJ political equipment as a real machine L'J'
are tears. This invention was made in order to deal with the above-mentioned 41Nf4, and its purpose is to integrate all or part of the JMt iShoto and iKiroku part, and to create a product IX'L in the -frequency band.
Painter No. 15'tr [6J-shaped art book No. 1g suitable for recording it2] by providing a self-recording device. This purpose V, multiple pixels arranged in a matrix *
*1-layer image section and each llI]I output from the imaging section
The analog signal for each cycle is converted into digital 11! The 7"4 digital l11] I elementary signal that can be output from the MD converter that converts to l1 episode/15 and the VD converter is converted to 6 for each system.
This is realized by a self-recording device equipped with a self-contained pixel memory. Hereinafter, an embodiment of the drawing method No. 1d recording apparatus according to the present invention will be described with reference to Drawing R. FIG. 4 is a block diagram of an embodiment. The solid body scanned by the driver 10, i! [8! The discrete output of mS I2 is sent to the preamplifier I4 as output signal 111i, 1. The length is pulled/J-seconded and made into a continuous 1g number, which is then manually fed into the VD Henkyuki 16. If the solid-state image sensor 12f has imaging pixels arranged in a matrix, it may be &, i ("I. For example, it may be an X-Y address type in which photoelectric conversion elements and switching elements are arranged in a matrix. , CCD, BBD
etc. 1g charge transfer type may also be used. Solid-state layer image system 12iI:j: For color imaging, it may be a single interline CCD with +t, G, B mosaic filters as shown in FIG. A two-plate type with G and R, 4, or a more R and G as shown in Figure 7. B It may be a three-plate type for each color. In the first embodiment, It. Each color contact number of G and B? - component signals are read out in 7 reals, so in the case of the mantissa board type, each color component signal is extracted as one pixel signal via the full nano 0 lexer 17. The φ converter 16 converts the output of the preamplifier Z4 into 8 for each pixel.
The pixel data is converted into a digital signal (1 byte) and recorded in the pixel memo I778. The A/D converter 16 samples and converts each pixel signal at the midpoint between the generation of the first signal and the signal output from the solid-state image sensor 12 in seven real times. In this way, since the signals of each pixel of the solid-state sensor 1 quadrant I2 are written to the pixel memory 18 in real time, yi>
The sampling frequency of the filter 16 may be the same as the driving clock frequency for the solid-state image sensor. For example, if the number of pixels of the solid-state image sensor 12 is 1000 x 1000, and the image capturing rate is 30 frames/second, the sampling frequency of the VD converter 16 is 30 MHz, and the current technology is sufficient. It is possible to realize it as a portable type. Kirani, R,G
, Bd' parallel N time readout, and if each color component signal is stored in the pixel memory, the sampling frequency for A/1) conversion can be 10 1z, which is 1/3. Since each pixel requires one byte, the size of the pixel memo IJ 1 B may be the number of bytes of pixels in the solid-state image sensor. 100OX 10
If the number of pixels is 00, it is 8M bits. Pixel memory 1
8 specifically, as shown in FIG. 8, the memories 1B-1, . It consists of a selector 44 that divides the memories into memories, and a multi-breather 46 that uses the outputs from the memories 1B-1, . . . , I8-8 as one signal. Each memory 1B-1, . . . , 18-8 is 1M bit. Memory 18-I is the bit of zt+,..., memory 18
-8 corresponds to 27 bits. That is, memory 1
In B-1, bit data of 2 degrees out of each pixel r is regularly stored in the pixel i. Note that the A/D converter 1
If 6 is a parallel output type, the selector 44il"i is not required. Note that a delay means such as a CCD annular register is provided after the preamplifier 14 to adjust the writing speed to the pixel memory 18 to the solid-state image sensor. It may be faster than the bladder ejection speed from Z2. In this way, the output fLI of the solid-state image sensor I2 is amplified through the Noriamp, and the processing or filtering etc. By replacing 10 power without one rubber and loading it into pixel memory 18,!V'D
The sampling frequency during conversion can be lowered, and the memory valleys and intersections can also be made smaller. For this reason, 0T
Even portable equipment can record high-quality video signals. Although the intended purpose can be achieved as is, the pixel memory I.
Preparing as many as 10 frames of 8 frames would result in high costs, so in reality, the signals are read out from the pixel memory 18 and re-recorded in a large-capacity memory. As large-capacity memory, magnetic tape, magnetic disk, optical-magnetic noise disk, CMOS memory, bubble memory, EEPROM, MNOS memory, etc. can be considered, depending on the volume/bit ratio, power consumption, operating speed, cost, etc. A magnetic disk is used here. Solid-state large-capacity memory (・-F 7” l MOIJ, C
MOS memo! (J, EEPROM, etc.), the higher the speed, the higher the power consumption and the higher the price including peripheral circuits. On the other hand, in the case of optical, magnetic, optical-magnetic, or other types of memories that involve relative movement, the faster the speed ratio, the larger the device becomes, and the write efficiency decreases. The starting signal from the pixel memory 18 is reproduced as the D/A i 1 δ. The speed at which pixels are read out from the pixel memory 7B and the operating speed of the D/A converter 2.theta. need not be high as long as they match the speed at which data is read into the large-capacity memory. Therefore, when the frequency characteristics of the large-capacity memory for re-recording are low, it is sufficient to take out the 1g thread from the pixel memo IJ 18 at a slower speed than when putting it in. In this way, by changing the frequency characteristics through the pixel memory midway, high-quality video in a high frequency band can be recorded on a conventional recording medium with low frequency characteristics. Driver 10. Solid-state image sensor 12, 'f') amplifier 14
, converter I6, pixel memory 18, D/A-z converter 20
The timing of each operation is controlled by the /stem controller 24. As shown in FIG. 9, the /stem controller 24 has a high frequency synchronous circuit z22 which serves as a reference for the operation timing up to overflow to the pixel memory 18, and a tI! tl
T'=1 It has a low frequency synchronization circuit 224 that serves as a reference for the operation timing after the bladder is ejected from the mortar 18. The output of the high frequency synchronous circuit 222 is supplied to the driver 10°, the solid-state virtual image element 12, and the preamplifier 14, and the clock 1 is supplied to the VD converter I6 via the VD converter controller 228.
Supplied as No. 6. High frequency, low frequency synchronous circuit 22
:l, 224 output, and the mode controller a-2230 that determines the read/write mode of the pixel memory I8 are supplied to the memory controller 232, and the output is sent to the pixel memory IJ1g as the clock number 1. Supplied. That is, the memory controller 232 inputs the output of the high frequency synchronization circuit 222 to the memory I when writing the memory.
When reading J, the output of the low frequency synchronization circuit 224 is supplied to the pixel memory 18. The output of the low frequency synchronization circuit 224 is supplied as a clock signal to the D/A converter 20 via the D/A K converter controller 234. Regarding the operation of the solid-state virtual image element 12, the operating clock frequency is first selected, and the frequency of the high frequency synchronization circuit 2220 is determined accordingly.Therefore, even if the operating mode of the image sensor changes, The recording thread up to the pixel memory 18 can cope with this.The output of the D/A converter 20 is subjected to synchronous addition, static and pattern noise reduction, duty smear reduction, etc. via the process amplifier 22, and is converted into a composite video signal. , recording circuit 2
The hat is offered on the 6th. -゛Recording time jNj26 includes an FM modulator and 1G Whale Anne 1, FM modulates the video 1st signal, and increases 1-
Magnetic head 28 through the LJJ switch 32K gold
and record it on the magnetic disk 30. Normally, the above-mentioned parts are housed within one electronic camera body, and the regeneration system is provided separately, but the regeneration thread may also be built into the main body. The reproduced video signal from the 4M air buoy disk 3θ is inputted to the reproduction circuit 34 via the magnetic ~\7)2 B, I, II conversion switch 32. The output of the reproduction circuit 34 is input to the A/D converter. 36, the frame memory 38 and the D/A converter 40 are operated to supply the interface circuit 42.The room memory 38, in contrast to the pixel memory 18, receives the video signal transmitted at a low speed and is read out by the converter. As a result, the frequency band of the video signal reproduced from the large-capacity memory is equal to that of the image sensor.The output of the interface circuit 42 is supplied to a CRT monitor, printer, etc., and a high-quality still image is converted into P+. As explained above, according to this embodiment, the output pixel signal of the virtual image portion is once stored in the pixel memory, and then
Since it is recorded in the memory, the frequency characteristics of the i-recording system can be lowered. As a result, even video signals based on high-definition video formats that require a frequency band several times larger than the current NTSC format can be recorded using devices with frequency characteristics as short as those of conventional NTSC formats. It is effective in some respects. Furthermore, the pixel memory of this embodiment has a smaller capacity than a conventional frame memory. Output 1 of solid-state virtual image element
The value of No. 6 itself is a j′ analog value, but the array of each pixel,
That is, the position information is digital. Therefore, this embodiment focuses on the fact that this position 1^ information is digital, and reduces the output pixel/1 signal of the 1 & image system as it is. Here, just the frequency characteristics? If this is the purpose, it is conceivable to completely slow down the output speed of the signal from the solid-state image sensor, but this is not preferable for the following reasons.If the indulgence time becomes too busy, The dark current of the element increases and the image quality deteriorates.With low-speed readout, the bladder extrusion image 1 does not become a moving image, which is not compatible with the operating speed of the external CR'l' monitor or electronic viewfinder, making it difficult to confirm the image. In addition, if the purpose is simply to reduce the memory capacity and increase the capacity, it is possible to compress the signal width, but this is not possible for the following reasons. Since the target is a still image, there is no correlation with the !jll frame, and compression using the frame correlation method is not possible.Since the target is the tI: intentional form, the image quality will be low if the 7'1 correlation is taken. 'In addition, the size of the peripheral circuit for compression increases.Also, we will reiterate the drawbacks of the conventional 6-track/stem system using frame memory 2.The number of bilateral relatives of 1rlf loops Double the memory byte a is required.Although the output 1st sign from the h411 element includes information on the 1st group of 1IiII elements, this is not used in the frame memory and the position information is stored in the form of coordinate transformation. , so that instability such as jitter increases.Additionally, an additional circuit for image restoration and video processing is required to compensate for this instability.On the other hand, in this embodiment, The use of the pixel memory is one-shot 1-information compression, which eliminates the 1N information spreadability in the use of the 71-nome memory. It can be said that this is similar to image recording using a CRT, in other words, fixing the position '+Nyl&, color, and intensity information of a chemical change caused by light at the location where the chemical change occurred. If the frequency characteristics of external devices such as monitors and printers do not deviate significantly from the frequency characteristics of the recording system, as shown by the broken line in Figure 4, the reproduction I@340 output is converted to A/1) converter I6, It may also be input manually to the interface circuit 42 via the pixel memory I8 and the D/A converter 20. As a result, A,/1) converter, 76, frame memo IJ, ?s, D/p,' l
Houki 4θ is omitted. However, in this case, 1+lII
Raw Me [Su Z8'? F II'L increases. Next, another embodiment of the invention will be described. The parts corresponding to those in the first embodiment are the same and the explanation will be omitted. FIG. 10 1j shows 4 lines in the diagram of the second embodiment. Item 52 Implementation 19 &j It
, G, 11/l)) - file reading is the same as in the first column of the first implementation, but the 6 self-recordings of the large-capacity memory can be read out. In Hakuri. l r! ? (11 is played with the original signal as it is.)
22 is I) in the 111 raw system from large capacity memory.
/A %H12-41: *Moxibustion continues to occur between 40 and interface circuit 42. According to this example, Hitotani 1
□The endogenous signal of T Meshirigashi was sent to the frame memory 38 before it was converted into Ei 1 Sui 1, 1 by F0 Rocess Anzo 22. 1-: of memory 38 is an expression of pixel memory ls, and even if frame memory is shared with pixel memory, 11
! The capacity of 11 elements will never be exceeded. FIG. 11 shows a block diagram of the third embodiment. In this example, R, G, B valley color components 1
A signal ωL is output from the solid-state image pickup device 12 in parallel and is input to the process amplifier 22, where it is processed as it is. The solid-state image sensor 12 is not limited to a three-plate type, and may be a single-plate type. Examples of single-chip cameras are shown in 12th to 1st.
Shown in Figure 4. FIG. 12 shows an X-Y address type camera. R, G, and B color filters are provided in a color line sequential manner for each horizontal scanning line section on a two-dimensional array of pixel regions. The area of each color filter is connected to selectors 66, 6 and 7θ, respectively, and each color line signal is read out simultaneously for the three colors. Figure 13 shows the interline method COD.
An example of a single-chip camera is shown here. This camera also has R, G, B (1) color filters provided for each horizontal scanning section in a color line sequential manner. Figure 14 shows a single-chip solid-state image sensor using a frame transfer CCD. 1"
It is. Contrary to the case in FIG. 15, R, G, and B filters are housed above the light filter section 166 in accordance with the vertical pixel columns xJ-L. Original 11J, change (generated in the central part 72, the electric charge of the /kotani l11!I element is transferred to the accumulation part 74Q in a batch, and each horizontal line is transferred from the /full resistor 6 for horizontal ?tjt output to Kl/ig. Diagnosis output δRei.l water jV lI for each eclipse line!Ll element 1g is R, G,
The color components of H are represented in a first order manner and change in a color point sequential manner. Therefore, the output of the register 76 is sent to each pixel Iσ via the selector 78 as R, L; , II color con? -Divided into component signals. This results in 1
The entire screen is evacuated one by one in color dots. Not limited to dot sequential readout vJ, frame A l transfer CCIJ, checkerboard color filter is used, XY-array type MO87' vice, interline vL C (I
) is also possible. In the case of simultaneous R, G, and B parallel readout, the readout speed of each component signal from the solid-state image sensor may be 1/3 of that in the case of realistic readout. As shown in FIG. 15, the memo I718 has three memories IB-1, 18-2 and 18 for each color component.
-,? is provided. Each memory 18-1.18-2.
18-. 1 is 8 memories 80-1 that store the 8-bit pixel signal resulting from the A-Oki transformation for each valley bit.
．． ..., 8os. Here, VI) The output of the vibrator 16 is given to each bit h. Assuming that it is output in parallel, selector e as shown in Figure 81S8 is unnecessary. Similarly, since the D/A converter 20 also has parallel input,
The multiplexer shown in FIG. 8 is also unnecessary. Now, if we assume that the number of pixels of the image sensor = il 125 (b) x 1398 αυ and each pixel is divided into 8 bits, how many pixels are there in each controller? -Memory for each component is 1125X1398X8XI/3
=4194000=2 -. It becomes 4M bits. Each memory 8 L) -1,..., 80-8 has a capacity of 5
-2 out of 24287 is 1524 k bits. The process amplifier 22 inputs human-powered R, G, and B signals at a brightness of 1 g.
@Y N Wideband, narrowband color II '18 cW, cN
No component #A'M. The Y, Cw, and CN components No. 1g are adjusted to F M i by the recording circuit 20 and are respectively magnetic-\nod 2B-.
1°2B-2, 28-3 are used for recording onto the magnetic disk F0. In this way, in the third fire example, t, 1, Y,
CW, CN Cond? -I don't like my first self-record in Nentjσ. The reproduction component signals from the magnetic heads 28-1.28-2.28-3 are shown in FIG. 74e (11).
Input into raw silk. In this embodiment, a black and white electronic video camera is provided for checking the recorded image.
After the number is Zorianno 014 all □ 1 tofu, process amplifier 5o and white 7. %l, J5 digital video signal, etc., and is supplied to the mf viewer/f blowfish 52. As a result, the image to be recorded is displayed in real-time on the electronic viewfinder. The electronic viewfinder 52 is C
RT. +14 is made up of LCI), LED, etc. Displaying high-quality images as they are in real time Q”, Sex 11
Although it is difficult in terms of time, cost and size, the above-mentioned method allows the current hQNTSCh type electronic broadcasting to be used. Note that if the purpose is simply to lower the output speed of the solid-state image sensor, that is, the sampling frequency of the ψ converter 16, there is no need to read out each color component, and the pixel chain of the image sensor It is also possible to divide the acid into an arbitrary number of subregions and process the output/activation signal of each subregion in parallel.In this case, the color filter array may be a striped filter structure, color point sequential, or color filter arrangement. It is also possible to use the line sequential method.
FIG. 6 is a block diagram of the fourth embodiment. This embodiment is an embodiment in which the recording method on the magnetic disk 30 of the third embodiment is changed (h'). Here, the output of the converter 20 does not pass through the process amplifier, but passes only through the recording circuit 26, ,R,
G. A B color component signal is recorded. According to this method, a brightness signal is not created by the process amplifier, so even if the readout speed of the pixel memory 18 is set to the same as the reading speed, the frequency of the recording system does not increase, making it difficult to record high-quality moving images. I also understand. FIG. 17 shows a fifth embodiment. In this embodiment, R, G, and B color component signals are processed in nine parallels until writing to the base memory I8. From pixel memory 18! 1'1 output R, G, B are multiplexer 7
2 is converted into a serial signal, and D/A conversion NZ 2'
, a process amplifier 22, and a recording circuit 26, and are recorded on a magnetic disk 30 by one magnetic head 28 as a component video signal. As explained above, the first aspect of the present invention is that the imaging section and the recording section are integrated, and the imaging section and the recording section are integrated, so that an image signal with a "b" carrier strength is suitable for recording all high-quality video signals in a high frequency range. A recording device can be provided. This invention is not limited to the embodiments described above, and can be modified in many ways. Not only high quality standards, but also current NTSC, PAL
The OJ function can also be applied to image signals of systems such as , SECAM, etc. 4. Brief description of the drawings Fig. 1 is a block diagram of a conventional stationary type high-quality image signal recording and reproducing device; 3
The figure shows the frequency outside the board, Figure 4e is a block diagram of an embodiment of the image signal recording device according to the present invention, and Figures 5 to 7 show examples of the configuration of the solid-state virtual image element in this embodiment. 8 is a block diagram showing an example of the image memory in this embodiment, FIG. 9 is a block diagram of the system controller in this embodiment, and FIG. 10 is a block diagram of the system controller in this embodiment. Glock diagram, FIG. 11 is a block diagram of the third embodiment of the present invention, FIGS. 12 to 14 are block diagrams showing configuration examples of the solid-state virtual image element in this third embodiment, and FIG. 15 is a block diagram of the third embodiment of the present invention. The block diagrams of the pixel memory in the embodiment, FIGS. 16 and 17, are the fourth and fifth blocks, respectively.
Let's take a look at the example Glock diagram. 12...Solid state J-Hani 1 collector, 18...Pixel memory,
22... Process amplifier, 26... Recording circuit, 30
...Magnetic disc, 34...Reproduction circuit, 38...
-Frame memory, 42...interface. Applicant's agent Patent attorney Wang Kun

Claims (5)

[Claims] (1) Two-dimensional Ma) An imaging means having a large number of photoelectric conversion elements arranged in an IJ shape, means for converting an output signal of the imaging means into a digital signal for each photoelectric conversion element, and a means for converting the output signal of the imaging means into a digital signal for each photoelectric conversion element; An image signal processing device comprising means for recording output. (2) Further comprising a re-recording means connected to the recording means, the recording means is set to have a reading speed slower than the evening speed, and the re-recording means has a larger capacity than the recording means. An image signal processing device according to claim 1. (3) The imaging means outputs a plurality of signals each having different color information, and the converting means and the recording means are each provided for each color information. The image signal processing device described (4) The recording device according to claim 1, wherein the recording device has a capacity equal to the product of the number of photoelectric conversion elements of the imaging device and the number of output bits of the conversion device. Image signal processing device. (5) The image signal processing apparatus according to claim 2, wherein the re-storage means is a magnetic recording means that operates in the frequency band of the NTSC television system.