JPS5933370U

JPS5933370U - Binarization processing circuit

Info

Publication number: JPS5933370U
Application number: JP12827382U
Authority: JP
Inventors: 西田　嘉夫
Original assignee: ミノルタ株式会社
Priority date: 1982-08-24
Filing date: 1982-08-24
Publication date: 1984-03-01

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図ａおよびｂは従来の２値化処理回路における動作
特性を表わすグラフ、第２図はこの考案を用いることが
できる画像読取装置の基本的構成を説明するための図、
第３図は、第２図の画像読取装置における画像読取領域
を示す図、第４図はこの考案の一実施例の２値化処理回
路図、第５図ａおよびｂは、第４図の処理回路における
主要構成部分の動作特性を示すグラフ、第６図はこの考
案の変形した一例の主要構成部分の回路図、第７図はこ
の考案のもう一つの変形例の主要構成部分の回路図であ
る。９・・・イメージセンサ、１０・・・ＣＣＤ駆動回路、
・１１・・・サンプルホールド指令用のパルス発生器、
１３−・・ビデオ増幅器、１４・・・サンプルホールド
回路、１６．１６’・・・第１積分回路、１８・・・第
１積分回路の抵抗、１９・・・第１積分回路のキャパシ
タ、２５．２５’、２５“・・・第一２積分回路、２７
・・・抵抗、２８・・・可変抵抗器、２９・・・第２積
分回路のキャパシタ、３２・・・信号加算用の抵抗、３
３・・・比較器。光λカ第４図1A and 1B are graphs showing the operating characteristics of a conventional binarization processing circuit, and FIG. 2 is a diagram for explaining the basic configuration of an image reading device that can use this invention.
FIG. 3 is a diagram showing the image reading area in the image reading device of FIG. 2, FIG. 4 is a binarization processing circuit diagram of an embodiment of this invention, and FIGS. A graph showing the operating characteristics of the main components in the processing circuit, FIG. 6 is a circuit diagram of the main components of a modified example of this invention, and FIG. 7 is a circuit diagram of the main components of another modification of this invention. It is. 9... Image sensor, 10... CCD drive circuit,
・11...Pulse generator for sample hold command,
13-- Video amplifier, 14... Sample and hold circuit, 16.16'... First integrating circuit, 18... Resistor of the first integrating circuit, 19... Capacitor of the first integrating circuit, 25 .25', 25"...first 2nd integration circuit, 27
... Resistor, 28... Variable resistor, 29... Capacitor of second integration circuit, 32... Resistor for signal addition, 3
3... Comparator. Light λ power Figure 4

Claims

[Claims for Utility Model Registration] A first integrating circuit that integrates an analog signal from an image sensor;
The output of the integrator circuit or the second integrator circuit that integrates the analog signal, and the signal obtained by combining the surface outputs of the first integrator circuit and the second integrator circuit are used as a threshold signal and are compared with the analog signal to determine the binary value of the analog signal. A binarization processing circuit comprising: a circuit for performing conversion processing.