JPS5933273B2 - Semiconductor light emitting device mounting equipment - Google Patents

Semiconductor light emitting device mounting equipment

Info

Publication number
JPS5933273B2
JPS5933273B2 JP54013587A JP1358779A JPS5933273B2 JP S5933273 B2 JPS5933273 B2 JP S5933273B2 JP 54013587 A JP54013587 A JP 54013587A JP 1358779 A JP1358779 A JP 1358779A JP S5933273 B2 JPS5933273 B2 JP S5933273B2
Authority
JP
Japan
Prior art keywords
light emitting
semiconductor light
emitting device
device mounting
mounting equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54013587A
Other languages
Japanese (ja)
Other versions
JPS55105390A (en
Inventor
清 白川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP54013587A priority Critical patent/JPS5933273B2/en
Publication of JPS55105390A publication Critical patent/JPS55105390A/en
Publication of JPS5933273B2 publication Critical patent/JPS5933273B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

【発明の詳細な説明】 本発明は半導体発光素子の取付け装置に関し、その取付
け高さを任意の高さに選択することができるようにした
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mounting device for a semiconductor light emitting device, which allows the mounting height to be selected as desired.

まず、従来のこの種装置について第1図、第2図を用い
て説明すると、1は半導体発光素子であり、2、3は金
属支持板である。
First, a conventional device of this type will be explained with reference to FIGS. 1 and 2. Reference numeral 1 is a semiconductor light emitting element, and 2 and 3 are metal support plates.

前記金属支持板2、3はそれぞれが対をなしてその複数
の対が連結板4により予め一体に形成されており、半導
体発光素子1は各金属支持板2、3上で銀ペースト等の
導電性接合材により接合および金線5等を用いてボンデ
ングにより接続されている。6は前記半導体発光素子1
を保護する保護樹脂である。
The metal support plates 2 and 3 each form a pair, and the plurality of pairs are integrally formed in advance by a connecting plate 4, and the semiconductor light emitting device 1 is coated with conductive material such as silver paste on each metal support plate 2 and 3. They are connected by bonding using a bonding material and by bonding using a gold wire 5 or the like. 6 is the semiconductor light emitting device 1
It is a protective resin that protects the

前記金属支持板2、3は前記半導体発光素子1を保護樹
脂6で保護した後、連結板4をプレス等で切断し、第2
図に示すように独立された金属支持板2、3に半導体発
光素子1が取付けられプこ部品として完成される。
The metal supporting plates 2 and 3 are formed by protecting the semiconductor light emitting device 1 with a protective resin 6, and then cutting the connecting plate 4 with a press or the like.
As shown in the figure, the semiconductor light emitting device 1 is attached to independent metal support plates 2 and 3 to complete the package.

このようにして完成された部品を印刷配線基板等に実装
する際、取付け面から比較的高い位置に5 半導体発光
素子1を位置させたい場合、金属支持板2、3をフォー
ミング加工したりして位置出しを行なつているが、これ
は非常に手間がかかり、また精度的にも難点があつた。
When mounting the components completed in this way on a printed wiring board, etc., if it is desired to position the semiconductor light emitting device 1 at a relatively high position from the mounting surface, the metal support plates 2 and 3 may be formed. Positioning was performed, but this was very time consuming and also had problems with accuracy.

また連結板の切断突起片4aをストッパーに利用する方
法も考えら10れるが、これはその取付け高さが必然的
に決定されてしまうため、半導体発光素子1を任意の高
さに選択することができないため、凡用性がなく、不都
合である。本発明はこのような従来の欠点を解消したも
の15であり、以下その一実施例について第3図、第4
図を用いて説明する。
Another possibility is to use the cut protrusion piece 4a of the connecting plate as a stopper10, but since this inevitably determines the mounting height, it is not possible to select an arbitrary height for the semiconductor light emitting element 1. Because it cannot be used, it is not versatile and is inconvenient. The present invention eliminates such conventional drawbacks15, and an embodiment thereof will be described below in FIGS. 3 and 4.
This will be explained using figures.

第3図、第4図において、第1、2図の従来のものと同
一構成部分には同一番号が附してあり、本発明は予め金
属支持板2、3を複数個の連結板20T、8、9、1O
、11で連結する。
In FIGS. 3 and 4, the same components as those in the conventional one shown in FIGS. 8, 9, 1O
, 11.

そして、この連結板T〜11の切断時、実装時の条件に
よりその連結板7〜11の残跡部を例えば第4図a、b
に示すように突起片Taとして残すか、ま、た9aとし
て残すかを選択することによ25り、この突起片Ta、
9aをストッパーに利用し、半導体発光素子1の取付け
高さを選択することができるものである。本発明は以上
のように、簡単な構成で半導体発光素子の実装時の取付
け高さを任意の高さに選択30することができるもので
あり、しかもその高さ位置は金属支持板の連結板の残部
突起片をストッパーに利用するという簡単な手段で設定
され、極めて安価に実施できるという効果を有するもの
である。
When the connecting plates T to 11 are cut, the remaining portions of the connecting plates T to 11 are cut, for example, in FIGS. 4a and 4b, depending on the mounting conditions.
By selecting whether to leave it as a protruding piece Ta or as a 9a as shown in 25, this protruding piece Ta,
By using 9a as a stopper, the mounting height of the semiconductor light emitting device 1 can be selected. As described above, the present invention allows the mounting height of the semiconductor light emitting device to be selected at any desired height with a simple configuration, and the height position is set at the connecting plate of the metal support plate. It is set by a simple means of using the remaining projection piece as a stopper, and has the effect that it can be implemented at an extremely low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示す連結板の切断前の状態の一部断面
正面図、第2図は同連結板の切断後の状?を示す一部断
面正面図、第3図は本発明の一実帷例の連結板の切断前
の状態を示す一部断面正面図、第4図A,bは同連結板
の切断後の状態をそミす一部断面正面図である。 ・半導体発光素子、2,3・・・・・・金属支持板、・
・・・・・連結板、7a99a・・・・・―突起片。
Fig. 1 is a partial cross-sectional front view of a conventional connecting plate before cutting, and Fig. 2 shows the state of the connecting plate after cutting. FIG. 3 is a partially sectional front view showing the connecting plate of an example of the present invention before cutting, and FIGS. 4A and 4B show the connecting plate after cutting. FIG.・Semiconductor light emitting device, 2, 3...metal support plate,・
...Connecting plate, 7a99a...-Protrusion piece.

Claims (1)

【特許請求の範囲】[Claims] 1 複数の連結板により一体となつた対をなす複数の金
属支持板上に半導体発生素子を取付け、かつ前記複数の
連結板を切断し、その切断による残跡部に突起片を選択
的に形成することにより前記半導体発光素子の実装高さ
を選択的に設定可能に構成してなる半導体発光素子の取
付け装置。
1. A semiconductor generating element is mounted on a plurality of metal supporting plates that form a pair that are integrated by a plurality of connecting plates, and the plurality of connecting plates are cut, and protrusions are selectively formed in the portion left by the cutting. A mounting device for a semiconductor light emitting element, wherein the mounting height of the semiconductor light emitting element can be selectively set.
JP54013587A 1979-02-08 1979-02-08 Semiconductor light emitting device mounting equipment Expired JPS5933273B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54013587A JPS5933273B2 (en) 1979-02-08 1979-02-08 Semiconductor light emitting device mounting equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54013587A JPS5933273B2 (en) 1979-02-08 1979-02-08 Semiconductor light emitting device mounting equipment

Publications (2)

Publication Number Publication Date
JPS55105390A JPS55105390A (en) 1980-08-12
JPS5933273B2 true JPS5933273B2 (en) 1984-08-14

Family

ID=11837312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54013587A Expired JPS5933273B2 (en) 1979-02-08 1979-02-08 Semiconductor light emitting device mounting equipment

Country Status (1)

Country Link
JP (1) JPS5933273B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6677614B1 (en) 1992-12-17 2004-01-13 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device
JP2809951B2 (en) * 1992-12-17 1998-10-15 株式会社東芝 Semiconductor light emitting device and method of manufacturing the same
US6808950B2 (en) 1992-12-17 2004-10-26 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing the device

Also Published As

Publication number Publication date
JPS55105390A (en) 1980-08-12

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