JPS5932039A - Generator of trigonometric function - Google Patents

Generator of trigonometric function

Info

Publication number
JPS5932039A
JPS5932039A JP57140711A JP14071182A JPS5932039A JP S5932039 A JPS5932039 A JP S5932039A JP 57140711 A JP57140711 A JP 57140711A JP 14071182 A JP14071182 A JP 14071182A JP S5932039 A JPS5932039 A JP S5932039A
Authority
JP
Japan
Prior art keywords
signal
word
output
trigonometric function
function value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57140711A
Other languages
Japanese (ja)
Inventor
Hajime Yoneyama
米山 元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57140711A priority Critical patent/JPS5932039A/en
Publication of JPS5932039A publication Critical patent/JPS5932039A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02Digital function generators
    • G06F1/03Digital function generators working, at least partly, by table look-up
    • G06F1/035Reduction of table size
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2101/00Indexing scheme relating to the type of digital function generated
    • G06F2101/04Trigonometric functions

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To obtain simply a trigonometric function value, by generating the tigonometric function value corresponding to an input digital signal in the form of a digital signal by a storage element of a comparatively small capacity and with accuracy approximately equal to that of a conventional process. CONSTITUTION:A parallel digital signal (x) is decomposed by a word decomposer 1 into high-order and low-order word signals (a) and (b). The word (a) is branched to two parts and supplied to a signal switch 3 and a phase converter 2, respectively. The converter 2 performs an operation of an output signal (c) as c=pi/2-a. The switch 3 uses its output (d) to deliver the signal (a) for a period from a time point t1 through t2 and then the signal (c) at and after the time point t2. A storage element 4 delivers the cosine function value e(cosa) to the signal (a) and the sine function value e(sina) to the signal (c) respectively. A multiplier 6 obtains a product (g) of a signal f(cosa) and the signal (b), and an adder 7 adds this product (g) with the signal (e). Thus it is possible to obtain an output signal y=sinx at and after the time point t2.

Description

【発明の詳細な説明】 本発明は、入力デジタル信号に対応する三角関数値をデ
ジタル信号の形で発生する。高精度で小記憶容量の電気
的三角関数発生器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention generates trigonometric function values in the form of digital signals corresponding to input digital signals. This invention relates to an electrical trigonometric function generator with high precision and small storage capacity.

一般に、すべての周期的な信号はフーリエ級数によって
三角関数に分解され、動的線型システム模擬装置等にお
いては、外乱等の入力とじて、三角関数発生器が欠かす
ことのできない構成要素となる。
In general, all periodic signals are decomposed into trigonometric functions using a Fourier series, and in dynamic linear system simulators and the like, a trigonometric function generator becomes an indispensable component when inputting disturbances and the like.

従来、三角関数値全デジタル値で発生するには入力角度
信号と対応したアドレスにその角度に対応した三角関数
値をあらかじめ計算して、@納された記憶素子が用いら
れ、入力信号をそのアドレスとして印加し、その内容を
読み出すことによって、入力信号に対応する三角関数値
が出方信号として得られる方法が一般的であった。
Conventionally, in order to generate a trigonometric function value as a fully digital value, a storage element is used in which the trigonometric function value corresponding to the angle is calculated in advance and stored at an address corresponding to the input angle signal, and the input signal is stored at that address. A common method was to apply a trigonometric function value corresponding to the input signal as an output signal by reading the contents.

したがって入力信号と記憶素子内のアドレスが1対1に
対応するため、高精度の三角関数値出方全得るためには
、膨大な記憶素子容tを必要とする欠点があった。
Therefore, since there is a one-to-one correspondence between the input signal and the address within the storage element, there is a drawback that an enormous storage element capacity t is required in order to obtain all highly accurate trigonometric function values.

本発明は、上記の欠点を解決し、比較的小容量の記憶素
子によって、従来の方法と同程度の精度金もつ三角関数
発生器全提供するものである。
The present invention overcomes the above-mentioned drawbacks and provides a complete trigonometric function generator with as much accuracy as conventional methods, but with a relatively small capacity storage element.

本発明による三角関数発生器は、並列デジタル信号であ
る入力角度信号を適当なピット位置で上位ワードと下位
ワードに分解するワード分解器と、その上位ワードの位
相全換える位相変換器と、この位相変換器の出力とワー
ド分解量出力の上位ワードとに切り換えるための信号切
換器と、この切換器の出力に対応する三角関数値を発生
させる記憶素子と、この三角関数値を一定時間記憶する
遅延回路と、この遅延回路出力と、ワード分解量出力の
下位ワードとの債ヲ計算する加算器、更に信号の流れ音
制御するタイミング回路とから構成される。
The trigonometric function generator according to the present invention includes a word decomposer that decomposes an input angle signal, which is a parallel digital signal, into an upper word and a lower word at appropriate pit positions, a phase converter that completely changes the phase of the upper word, and a phase converter that completely changes the phase of the upper word. A signal switch for switching between the output of the converter and the upper word of the word resolution output, a storage element that generates a trigonometric function value corresponding to the output of this switch, and a delay that stores this trigonometric function value for a certain period of time. It consists of a circuit, an adder that calculates the bond between the output of this delay circuit and the lower word of the word decomposition amount output, and a timing circuit that controls the flow sound of the signal.

次に本発明の実施例について図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

先ず、本発明の実施例全第1図並びに第2図を参照して
説明する。なお第2図では理解を容易とするため、加減
算器及び乗算器の時間遅れは記載しないものとした。
First, an embodiment of the present invention will be described with reference to FIG. 1 and FIG. 2. Note that in FIG. 2, time delays of adders/subtractors and multipliers are not shown for ease of understanding.

この例は、正弦関数値全発生させる関数発生器の例であ
る。即ち、入力デジタル角度信号Xが与えられ y=sinx なるyをデジタル信号として、出力する関数発生器であ
るとする。
This example is an example of a function generator that generates all sine function values. That is, it is assumed that the function generator is given an input digital angle signal X and outputs y such that y=sinx as a digital signal.

第1図において並列デジタル信号Xは、第2図における
時刻t1にワード分解器1に入力され、ワード分解器1
によって固定のピット位置で上位ワード信号aと下位ワ
ード信号6に分解される。
In FIG. 1, the parallel digital signal X is input to the word decomposer 1 at time t1 in FIG.
is decomposed into an upper word signal a and a lower word signal 6 at a fixed pit position.

本ワード分解器1は、具体的には単に入力信号Xの並列
信号線全上位側と下位側に分解することで容易に実現で
きる。ワード分解器1より出力された上位ワード信号a
は二つに分岐し、その一方は信号切換器3に入力され、
他方は位相変換器2に入力される。
Specifically, this word decomposer 1 can be easily realized by simply decomposing all the parallel signal lines of the input signal X into upper and lower sides. Upper word signal a output from word decomposer 1
is branched into two, one of which is input to the signal switch 3,
The other is input to the phase converter 2.

位相変換器2は、その出力信号Cが C=π/2−a  (アシアン) となるような演算を行う。本位相変換器はあらかじめ入
力信号が0〜π/2 (アシアン)となるようにしてお
けば、単に高低の論理レベルを逆転するだけで容易に実
現できる。
The phase converter 2 performs an operation such that its output signal C becomes C=π/2-a (Asian). This phase converter can be easily realized by simply reversing the high and low logic levels by setting the input signal to be 0 to π/2 (Asian) in advance.

信号切換器3は、その出力dとして、時刻1゜から時刻
t2の間は信号aを、時刻t2以降は信号cTh出力す
るように、第2図の制御信号りによって制御される。
The signal switching device 3 is controlled by the control signal shown in FIG. 2 so as to output the signal a as its output d from time 1° to time t2, and output the signal cTh after time t2.

かくして入力角度信号の上位ワードaは、時刻t1と時
刻t2の間1cdを通じてあらかじめアドレス値に対応
する余弦関数値が格納されている記憶素子4のアドレス
として印加され、aに対応した余弦関数値e (cos
a)が出力され、遅延回路5に入力される。
Thus, the upper word a of the input angle signal is applied as an address to the storage element 4 in which the cosine function value corresponding to the address value is stored in advance for 1 cd between time t1 and time t2, and the cosine function value e corresponding to a is applied. (cos
a) is output and input to the delay circuit 5.

一方、時刻t、以降の信号切換器出力dは、前述したよ
うに位相変換器出力Cであり、記憶素子4のアドレスと
して印加される。よって時刻t!以降の記憶素子4の出
力eは e=cosd=cosc=cos(x/2−a)=si
naとなシ、正弦関数値(sina)  となる。
On the other hand, the signal switcher output d after time t is the phase converter output C, as described above, and is applied as the address of the memory element 4. Therefore, time t! The subsequent output e of the memory element 4 is e=cosd=cosc=cos(x/2-a)=si
When na and shi, the sine function value (sina) is obtained.

また、時刻1.以降遅延回路5よシ出力された余弦関数
値f (cosa)は前述のワード分解量出力の下位ワ
ード信号すとともに乗算器6に入力され、乗算器6は信
号fと、信号すのfRを計算する。
Also, time 1. Thereafter, the cosine function value f (cosa) output from the delay circuit 5 is input to the multiplier 6 along with the lower word signal of the word decomposition amount output, and the multiplier 6 calculates the signal f and the signal fR. do.

この積信号gは、一方の入力信号がeである加算器4に
入力として接続され、和をとられ、時刻t2以降出出力
器yとなる。
This product signal g is connected as an input to an adder 4 whose one input signal is e, is summed, and becomes an output/output device y after time t2.

この出力信号yが入力信号Xの正弦関数値になることは
、以下の議論より明白である。
It is clear from the discussion below that this output signal y is a sine function value of the input signal X.

一般にXの関数値f (x) t yとしてティラー展
開すると、 y=f(x用f(xt +X2 ) 中f(xs )+f’ (Xi )−Xl正弦関数の場
合、第2図の信号名に対応して書き改めると、 y=sinx さらに第2図全考慮に入れると 時刻t1と時刻t2の間 C二π/2−a d=a 時刻t2以降 C−π/2−a d=c e=COS C=S 1 n  a f=cosa g=f11b−CO5a11b y=e+g=sina+cosaeb        
 (2)とな坦2)式は(1)式と一致する。
In general, if we perform Tiller expansion as the function value f (x) t y of X, then y = f (f for x (xt + Rewritten to correspond to y=sinx Furthermore, taking into account everything in Figure 2, between time t1 and time t2 C2π/2-a d=a After time t2 C-π/2-a d=c e=COS C=S 1 n a f=cosa g=f11b-CO5a11b y=e+g=sina+cosaeb
Equation (2) and Nada 2) match equation (1).

なお、加減算器及び乗算器の時間遅れを考慮に入れると
、出力yは第2図の時刻t3以降に採取すればよい。
Note that, taking into account the time delay of the adder/subtractor and the multiplier, the output y may be sampled after time t3 in FIG. 2.

また、信号切換器3の出力dが時刻11と 時刻t8の
間で信号Cとなり、時刻t2以降信号aとなるようにし
、加算器7での演算が y=e−g となるようにすれば、出力yは y=e−g =cosa−sina−b 中cos(x) となり、容易に余弦関数発生器へ転換できる。
Also, if the output d of the signal switch 3 becomes the signal C between time 11 and time t8, and becomes the signal a after time t2, the calculation at the adder 7 becomes y=e−g. , the output y is y=e−g=cosa−sina−b in cos(x), and can be easily converted to a cosine function generator.

以上説明したように、本発明によれば、正弦関数の微分
は余弦関数となシ、余弦関数の微分は正弦関数となるこ
とを利用して一次内挿により三角関数値を求めることが
簡単に可能となるので、読み出し専用の記憶素子音用い
た三角関数発生器において、記憶素子容量が小さくしか
も高精度の三角関数発生器の製作を可能とする効果を有
する。
As explained above, according to the present invention, trigonometric function values can be easily determined by linear interpolation by utilizing the fact that the differential of a sine function is a cosine function, and the differential of a cosine function is a sine function. Therefore, in a trigonometric function generator using a read-only storage element consonant, it is possible to manufacture a trigonometric function generator with a small storage element capacity and high accuracy.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すプロ、り図。 第2図は第1図に示される各信号の基本タイミングチャ
ートである。 1・・・・・・ワード分解器、2・・・・・・位相変換
器、3・・・・・・信号切換器、4・・・・・・記憶素
子、5・・・・・・遅延回路、6・・・・・・乗算器、
7・・・・・・加算器、8・・・・・・タイミング回路
FIG. 1 is a schematic diagram showing an embodiment of the present invention. FIG. 2 is a basic timing chart of each signal shown in FIG. 1... Word decomposer, 2... Phase converter, 3... Signal switch, 4... Memory element, 5... Delay circuit, 6...multiplier,
7... Adder, 8... Timing circuit.

Claims (1)

【特許請求の範囲】[Claims] 並列デジタル信号で与えられる入力角度を適当なビット
位置で上位ワードと下位ワードに分解するワード分解器
と、その上位ワードの位相を換える位相変換器と、この
位相変換器出力と前記上位ワードとを切刃換え出力する
信号切換器と、この信号切換器の出力に対応する三角関
数値を発生させる記憶素子と、この記憶素子から発生さ
れる三角関数値全一定時間記憶する遅延回路と、この遅
延回路出力と前記ワード分解器出力の下位ワードとの積
を計算する乗算器と、この乗算器出力と前記記憶素子か
らの三角関数値の和を計算する加算器と、前記各構成部
間における信号の流れを制御するタイミング回路とから
構成され、−次内挿処理をその基本原理とする並列デジ
タル型三角関数発生器。
A word decomposer that decomposes an input angle given by a parallel digital signal into an upper word and a lower word at appropriate bit positions, a phase converter that changes the phase of the upper word, and a phase converter that converts the output of this phase converter and the upper word. A signal switch that outputs a cutting blade, a storage element that generates a trigonometric function value corresponding to the output of this signal switch, a delay circuit that stores all the trigonometric function values generated from this storage element for a certain period of time, and this delay. a multiplier that calculates the product of the circuit output and the lower word of the output of the word decomposer; an adder that calculates the sum of the multiplier output and the trigonometric function value from the storage element; and a signal between each of the components. A parallel digital trigonometric function generator whose basic principle is -order interpolation processing.
JP57140711A 1982-08-13 1982-08-13 Generator of trigonometric function Pending JPS5932039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57140711A JPS5932039A (en) 1982-08-13 1982-08-13 Generator of trigonometric function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57140711A JPS5932039A (en) 1982-08-13 1982-08-13 Generator of trigonometric function

Publications (1)

Publication Number Publication Date
JPS5932039A true JPS5932039A (en) 1984-02-21

Family

ID=15274938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57140711A Pending JPS5932039A (en) 1982-08-13 1982-08-13 Generator of trigonometric function

Country Status (1)

Country Link
JP (1) JPS5932039A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9757857B2 (en) 2014-08-13 2017-09-12 Seiko Epson Corporation Piezoelectric driving device and driving method thereof, robot and driving method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9757857B2 (en) 2014-08-13 2017-09-12 Seiko Epson Corporation Piezoelectric driving device and driving method thereof, robot and driving method thereof

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