JPS5931744B2 - MOS digital computer - Google Patents

Description

[Detailed description of the invention] The present invention relates to the field of MOS computers.

MOS computers and bipolar multichip digital computers are known. For example, multiple chip bipolar microprocessors and single chip MOS processors are commercially available. However, to make a complete computer from a single chip MOS processor, several other chips are required. Typically, separate chips are required for program storage, "scratchpad" memory, or other functions. By reducing the number of chips needed to make a computer, the cost of the computer is reduced, compatibility problems are reduced, and cycle times can be easily increased. Multi-chip computers are too expensive and complex for many simple digital computer applications, such as in automobiles, household appliances, and many other applications. Ideally, many such applications require a single-chip digital computer that includes a program storage device. Several problems arise in building an entire computer on a single chip or board.

For example, in conventional computers, the program memory can be easily separated from the central processing unit (CPU), thereby allowing the CPU and program storage to be tested independently. However, if the CPU and program storage device are provided on the same chip, it becomes difficult to test the program storage device and the CPU independently.
Another problem arises when erasable programmable read only memories (PROMs) are used in single chip computers. Such PROMs require programming voltages that are significantly higher than those used during computer operation, and such programming voltages can corrupt the computer's multiplier. To implement a single-chip MOS computer, "scratch pad" registers must be used with maximum efficiency.

The reason is that scratchpad registers occupy a fairly large amount of chip area compared to other circuits in a computer. As will be apparent from the description of this specification, the present invention provides an erasable PROM on a single MOS chip.
It provides an all-MOS computer including:

Random access memory (RAM) used in high efficiency constitutes "scratchpad" storage. According to the invention, a MOS digital computer is obtained which is completely contained on one substrate.

The computer includes a bidirectional data bus having terminals for coupling to external circuitry. perform arithmetic functions,
A CPU for controlling the overall operation of the computer is connected to the data bus. RA connected to data bus
M is used to store data inside the computer.

Program bytes are stored in read-only memory (hereinafter referred to as ROM) coupled to the CPU and data bus. The CPU has a ROM and a program counter connected to the data bus. When the count in the program counter exceeds a predetermined count, the program counter provides an address signal to a board terminal connected to an external storage device. In this way, the computer's program storage capacity can be expanded through the use of external storage that is automatically addressed by the computer's program counter. Hereinafter, the present invention will be explained in detail with reference to the drawings.

The present invention provides an integrated circuit, MOS (metal monoxide semiconductor) digital computer that is completely contained on a single silicon substrate. This computer includes a CPU, RAM, and PROM for storing computer instructions. The computer shown in FIG. 1 includes a PROM12 connected to a bidirectional main data bus 25, a RAM14,
CPU16, and is formed on one substrate 20. This 8-wire data bus connects 8-bit CPU16 and RAM
In addition to being coupled to I4 and PROM I2, it is also coupled to external circuitry via multiple input/output ports.
In the embodiment described here, the computer is implemented with an n-channel MOS device using polycrystalline silicon gates. In order to run this computer,
Only one power supply (5 volts) is required other than the programming power supply. This computer processes more than 70 instructions, most of which are single-cycle instructions, with an instruction execution time of 2
~6 microseconds. Detailed technical matters regarding computers are well known, and their description in this specification would complicate the explanation and obscure the novelty of the present invention, so they will not be described in this specification. Omitted.

It will be appreciated, however, that while necessary computer techniques are described to illustrate the novel features of the computer of the present invention, they are not particularly necessary for practicing the present invention. In Figure 1, the ground wire Vss, etc.
Some of the input and output lines are shown. During normal operation (without programming), this computer:
One type of (positive) 5V power supply Vcc is used. While the computer is in operation, this 5V voltage is also applied to the VDD line.
However, during operation of PROMl2, a voltage of 25V is applied to the VDD line. The computer shown in FIG. 1 includes three 8-bit data buses.

These data buses are bidirectional main data buses 25 and 2.
The "pseudo" bidirectional data buses 15, 17 of the book.
The buffer amplifiers used for each bus bar 15, 17 will be explained with reference to FIG. The eight lines of main data bus 25 can be used synchronously to write information to or read information from the computer. A strobe wire (not shown) is used for this purpose. Other lines coupled to the computer shown in FIG. 1 include line 1 which receives a programming pulse of about 25V applied to PROM1
3 is included. A timing signal is applied to line 36 to enter the external address into the program counter. A pair of wires 1 to add timing signals to the computer
1 is used. This timing signal is a crystal oscillator, R
It can be generated using a C oscillator or the like. However, since the computer includes its own oscillator and clock circuit, an external frequency source is only needed for synchronization. In this computer, an instruction cycle consists of five types of states, and each state requires three types of oscillation periods.
Therefore, for a 5.0 microsecond instruction cycle, 3M
A Hz input signal is provided on line 11. The EA signal is provided to the computer via line 19. This EA signal will be explained with reference to FIG. Other input lines to and output lines from the computer not shown in FIG. 1 include a power on clear line, a sync output line, and other lines. CPU16 performs standard arithmetic operations and computer control functions.

Therefore, conventional circuitry can be used for this unit. This unit includes an arithmetic logic unit (hereinafter referred to as ALU) for performing addition operations, exclusive OR operations, logic AND operations, logic OFF operations, and shift operations. C.P.
U contains a 12-bit program counter. This counter will be explained in detail with reference to FIG. The CPU includes other known circuitry such as an instruction decoder, port controllers, stack pointer registers, RAM address registers, and their associated logic.
These will be explained in detail with reference to FIG. In the embodiment described here, RAMl4 comprises static MOS RAM used for internal data storage.

The capacity of this RAM is 64 pixels arranged in a 16x32 array.
8-bit words. For purposes of discussion here, RAM
l4 is 64 8-bit registers R. -R63. Eight of them are registers R. −
R7 is directly addressable and all registers are register R. can be indirectly addressed from R1. register R8
~R23 can be used for address stack storage to allow the CPU to keep track of return addresses generated from call instructions and interrupts.

The 3-bit stack pointer register 72 (FIG. 3) is
Provides the address where the next return address should be loaded.

The "push down" stack pointer register is incremented by a binary one after the return address is stored and decremented by a binary one before the address is retrieved. The stack registers used here allow a total of 8 levels of nesting.
ing) configuration is possible. (Note that since 12 bits are required to address a PROM, two registers in RAM14 must be used for storing a single PROM address.) Therefore, the stack If the pointer is incremented or decremented by 1, the actual address pointed to by the stack pointer is 2.
Only moved. If eight levels of nesting are not required, registers R8-R23 that are not used for other purposes as described below may be employed. RAM14
Registers R24 to R3l are registers R.

~ Can be directly addressed with the bank switching device in a similar manner to R7. This bank switching device will be explained with reference to FIG. Register R32~
R63 is used for any computer storage required. PROM12 is used to store 1024 8-bit instructions (i.e., program storage bytes containing instructions and fixed information, hereinafter referred to collectively as instructions) and has a 128.times.64 array.

In the embodiment described herein, each storage element or cell of the array includes a MOS device having a floating gate completely surrounded by oxide. Information is stored in each MOS device in the form of electrical charge. Those charges are injected into the floating gate by electron avalanche injection. The entire PROM12 can be erased by irradiating the substrate 20 with ultraviolet light, thereby discharging the floating gate. Such erasable floating gate devices are disclosed, for example, in U.S. Pat. No. 3,797.
, 000. Double polycrystalline silicon technology is adopted for the fabrication of PROMl2. The special method used to fabricate PROMl2 was introduced in January 1975.
US Patent Application No. 62 filed by the applicant on October 29th
No. 6,859. The self-aligned double crystal MOS fabrication method disclosed in this U.S. patent application allows the use of a single operating voltage (5V) while reducing the area of each storage element compared to conventional floating gate devices. can. Although a PROM is employed in the embodiment described herein, a ROM may be used, especially after a computer program has been developed.

Instead of PROM12, a ROM can be made on the chip. Refer now to FIG. This figure shows the PROM12 shown in FIG.
Shown above 0. In the embodiment described here, the program counter 2 consists of a 12-bit counter.
7 provides the address via bus 30 to the decoder portion of PROM12. The most significant and next bit of counter 27 is coupled via line 50 to one input terminal of OR gate 45. Program counter 27 is also coupled to bus 25 so that it can receive address signals from bus 25 and can send 8-bit signals to off-chip program storage 22 via bus 25. As explained in more detail later, when instructions are retrieved from off-chip,
Eight bits of the address are carried on bus 25 and the remaining four bits from program counter 27 are carried on eight line bus 15.
It is sent to off-chip storage 22 via four of the lines. PROMl2 in Fig. 2 is the switching device 2.
9 to bidirectional data bus 25.

This switching device 29 connects the PROM12 to the bus 25.
used to interrupt the flow of information to Another switching device 31 coupled to bus bar 25 is
is selectively coupled to an output port to couple bus 25 to external circuitry, such as storage device 22. The switching devices 29 and 31 are normally closed, and the AND gate 46
and 47, and are controlled by AND gates 40, respectively.
EA (external address) line 19 is the third state level detector 3
3, inverter 41, and the set terminal of flip-flop 35. The output terminal of inverter 41 is coupled to the clear terminal of flip-flop 35, and the Q output terminal of flip-flop 35 is coupled to one input terminal of OR gate 45. The output terminal of third state level detector 33 is coupled via line 51 to one input terminal of AND gates 47 , 48 and to the input terminal of inverter 42 . The output terminal of this inverter 42 is an AND gate 40
, 46 input terminals. The output terminal of the OR gate 45 is connected to the other terminal of the AND gate 46 and the inverter 44.
is combined with. The output terminal of this inverter 44 is coupled to the other input terminal of AND gate 40. A third state level detector 33, shown in FIG. 4, detects the level of voltage present on line 19 and provides a third state signal (25V).

If the signal present on line 19 is 0V (EA=O) or 5V (
EAL), the detector 35 produces almost no output. An instruction register 37 is coupled to the main bus 25 .

This instruction register 37 is coupled to an instruction decoder 39. This instruction decoder 39 accepts instructions from PROM12,
It is used to decode instructions applied to bus 25 from the outside. The instruction decoder 39 is connected to the C
It is coupled to circuits such as the ALU, port controller, carry logic, etc. within PU16. The output terminal of instruction decoder 39 is coupled to input line 19 via line 26. Line 26 is line 2
Line 26 is cut in the middle to show that it is not necessary to couple 4 to input line 19 directly, but rather through an intermediate circuit. To explain in detail later, decoder 3
9 can provide a signal to line 19. This signal causes instructions to be retrieved from off-chip storage, such as program storage 22. A timing signal applied to line 36 is used to load program counter 27 with an externally applied address to test the contents of PROM12.

Line 36 is directly connected to another input terminal of AND gate 48 and is coupled via inverter 43 to another input terminal of AND gate 47 . The output terminal of AND gate 48 is coupled to program counter 27 to input the address (8 bits from line 25 and line 3) to the program counter 27.
4 bits from 0) is to be loaded. The output terminal of the AND gate 47 is coupled to the switching device 29 so that, while the program counter 27 is being given an address from the outside, the output terminal of the AND gate 47 is connected to the main bus 25 from the PROM.
give a signal to prevent information from being given to Second
The various circuits shown in the figures, such as AND gates, OR gates, inverters, flip-flops, switching devices, and registers, are conventionally known circuits.

In order to facilitate understanding of the novel features of the computer of the present invention, the circuit shown in FIG. 2 has been simplified and signal paths and logic devices other than those shown have been omitted. be. But they are all well known. Assume that PROM12 is now programmed, the computer is running, EA2O, and the count of counter 27 is less than or equal to 1024.

If no signal is present on line 19, flip-flop 3
5 is set and a low level output appears at its Q terminal, no signal is applied to one input terminal of OR gate 45. Since the count of the counter 27 is less than 1025, no signal is applied to the other input terminal of the OR gate 45, so that no output appears at the output terminal of this OR gate 45. For this purpose, the switching device 29
remains closed, thereby coupling PROM12 to bus bar 25. Further, the outputs of the inverters 42 and 44 become high level and provide an output to the gate 40.
Then, the switching device 31 is opened and the main bus 25 is disconnected from the external signal. In this way, if the count of the program counter 27 is 1024 or less,
When EA=0, the program counter 27 is PROM
Take out the command from l2. When the count of program counter 27 exceeds 1024, line 50
A signal is given to the OR gate 45 via.

This signal produces an output at gate 45. This output, together with the signal from the inverter 42, is sent to the AND gate 46.
is added to switch 29 via
open. The output of gate 45 is inverted by inverter 44 to eliminate the single signal applied to gate 40. For this purpose, the switching device 31 couples the main bus 25 to the output port of the computer. In this way, when the count of the program counter 27 exceeds 1024,
Counter 27 automatically retrieves instructions from off-chip storage 22. When the signal on line 50 is removed (the count in the counter is less than 1025), PROM12 is recoupled to bus 25 and switching device 31 disconnects main bus 25 from external program storage 22.
Assuming EA=1, flip-flop 35 is allowed to change state.

Flip-flop 35 then gives a signal to OR gate 45 to open it. 5V present on line 19 (EA=1
) is insufficient to generate an output from the third state level detector 33, so the inverter 42
The signal at the output terminal of is kept at a high level K. Under these conditions, an output signal is generated by AND gate 46. This output signal opens the switching device independently of the state of program counter 27. The output of OR gate 45 is inverted by inverter 44 and then closes AND gate 40. To this end, the switching device 31 couples the main bus 25 to the output port of the computer. In this way, externally generated commands can be applied to the computer, and the computer's response to those commands can be applied to lines such as main bus 25, or other lines such as busses 15 and 17 in FIG. You can check it out. In this way, CPU16 and R shown in FIG.
AMl4 can be tested separately from PROMl2. line 19
The signal applied to can be initiated within the computer as shown by line 26. In this mode of operation,
Instructions stored externally can be taken out by the counter 27 or added from the outside independently of the counter 27. 5 or more (25 in the example described here)
Assume that a signal of V) is applied to line 19.

Third state level detector 33 then detects this signal and provides an output signal on line 51. This output signal is inverted by inverter 42 and then inhibits generation of the output signal of AND gate 46. Switching device 29 is therefore prevented from opening by AND gate 46. The output signal from the third state detector 33 also prevents the switching device 31 from being opened by the gate 40. Assuming no signal is present on line 36, an output signal is produced at the output terminal of AND gate 47. The output signal causes the switching device 29 to disconnect the PROM12 from the bus 25. Under such conditions, an external address can be applied to program counter 27 via buses 25 and 30 (via bus 15). When a signal is applied to line 36, an output is generated by AND gate 48 which causes the address to be loaded into counter 27. At the same time, when a signal is applied to line 36, the signal is removed from the output terminal of AND gate 47, thereby disconnecting PROM12 from bus line 25. In this way, externally applied addresses can be used to retrieve instructions from PROM12 and to check (externally) the retrieved instructions on bus 25.
This mode of operation allows the PROM to be tested. Thus, the circuit shown in FIG. 2 allows the program counter to be used to retrieve instructions from PROM12,
When the capacity of PROM12 is exceeded, instructions are automatically retrieved from an external storage device.

Furthermore, this same circuit can connect PROM or CPU to R.
Either AM can be tested separately. Refer now to FIG.

RAM 14 shown in FIG. 1 is again shown in this figure, with its read/write buffer coupled to the RAM's input/output bus 83. This 8-wire bus 83 is coupled to a switching device 70, which connects the 6 wires of this bus (bus 8
2) is coupled to multiplexer 74. The computer's bidirectional main bus 25 is coupled to a switching device 70 which allows data on bus 25 to be written to RAM 14 and data in RAM 14 to be read to bus 25. Make it.

For example, data from ALU 9l can be written to RAMl4, and data from RAMl4 can be written to ALU9l. RAMl4 is RAM address register 76
Receive address from.

This 6-bit address is stored in 64 8-bit registers R.
. - coupled to the decoder of the RAM for selecting one of R63; The input to RAM address register 76 is the output of multiplexer 74. This multiplexer receives switching signals from the instruction decoder.
Select one bus from the bus lines and store the signal on that bus in RAM.
Coupled to address register 76. multiplexer 7
4 selects a signal on one of the 6-line buses 80, 81, or 82. Line 71 of bus 81, which is coupled to the instruction decoder, provides the least significant bit of the RAM address. This bit allows the address to be selectively shifted by 1, allowing the 12-bit address from the program counter to be shifted to RA.
Allows storage in two consecutive registers in M14. Three bit stack pointer register 72, coupled to bus 25 by line 85, provides two bits of the address signal on line 88 and the other bit of the address signal on line 89. The signal applied to line 89 is inverted before being applied to line 90. The last line of bus 81 carrying the most significant bit of the address is grounded to provide a binary O. A third input bus 80 to multiplexer 74 includes three lines from main bus 25 and two lines 86 .

Both lines contain either a binary O or a 1. Bus line 8
The line carrying the most significant bit of zero is grounded to give a binary O. Switching device 70, stack pointer register 72, flip-flop 78, multiplexer 74, register 76, and ALU 9l can be constructed from known MOS circuits.

As mentioned above, register R of RAM14.

, Rl can be used to indirectly address other registers of RAMl4. Assume that an address is stored in one of those registers.
This address is applied via buses 83 and 82 to register 76, and from there to multiplexer 74 and register 76.
is applied to the RAM decoder via the RAM decoder. In this way, any register in RAM 14 can be called by the address stored in that RAM. 8 registers R to increase computer code efficiency.

-R7 can be directly addressed. The symbol needed to select any of those eight registers is bus 25
via line 92 from . The signals applied to those three lines are the three least significant bits of the RAM address. However, assume that all eight directly addressable registers store information, and that additional information is stored in RAM. The instruction decoder then provides a signal to flip-flop 78 causing it to add a binary 1 to line 86. Those signals applied to lines 86, the fourth and fifth bits of a 6-bit address, add 24 bits to the address.
Add.

Therefore, flip-flop 78 is set and the address of main bus 25 is R. If we choose R
Data applied to AM (RAM bus 83) is stored in register R24. Similarly, assuming that the address on bus 25 selects register R8 and flip-flop 78 is set, data applied to RAM will be stored in register R3. Thus, in order to directly address 8 registers, only 3
Although only bits are used, by using flip-flop 78, 16 registers can actually be directly addressed. Three lines 85 provide addresses for storing the contents of the program counter.

As discussed herein, the high/low line 87 causes the first eight bits of the address to be stored in one register and the remaining bits of the address to be stored in adjacent registers. By the signals applied to lines 89 and 90,
Addresses on bus 81 are made to select registers R8-R23. However, because all registers in RAM are indirectly addressable, registers R8-R23 can be used for other storage devices that do not require eight levels of nested organization. Next, refer to FIG. In this example,
The third state level detector 33 has a pair of transistors 120 and 121 coupled in series. transistor 120
The drain and gate of are coupled to the input line 19 and the source is coupled to the output line 51 of the third state level detector 33.
Transistor 121 is coupled between output line 51 and ground. The gate of transistor 121 is coupled to voltage source Vcc. Since the length of the channel of transistor 120 is approximately five times that of the channel of transistor 121, the internal resistance value of transistor 120 when it is conductive is sufficiently larger than the internal resistance value of transistor 121 when it is conductive. When a voltage of 5V (EA=1) is applied to input line 19, transistors 120 and 121 are both conductive, but the output appearing on output line 51 is well below 1. Therefore, for the circuit shown in FIG. 2, this voltage is not sufficient to act as a high level input to the gate or inverter. When a third state voltage of 25V is applied to line 19, transistor 121 becomes fully saturated and is overloaded by transistor 120 to raise the potential of output line 51 to about 10V. This potential is a high level signal for the gate and inverter. As mentioned above, the busbars 15 and 17 shown in FIG. 1 are "pseudo" bidirectional, so that they appear to be bidirectional from the outside.

However, each line of those buses includes separate input and output lines between the buffer and the rest of the computer. This buffer allows you to obtain a buffered output,
And external inputs can be added to the input/output ports. Refer now to FIG.

Each port has a pad 100, an input line such as line 118 to the buffer (output from the computer), and an output line such as line 119 from the buffer (input to the computer).
including. The signal on output line 119 is the complement of the input signal applied to pad 100. Man pad 100 is coupled to circuit point 113. This circuit point is coupled to Cc via depletion mode transistor 101. The resistance of this transistor is relatively high, and the circuit point 113
When charged through pull-up transistor 105, it is used to maintain node 113 at Cc potential. The gate of transistor 105 is coupled to node 114 . This circuit point 114 is coupled to Cc via depletion mode transistor 108 and
Grounded via parallel transistors 109 and 110.
The gate of transistor 109 is coupled to the φ signal source and the gate of transistor 110 is coupled to circuit point 115. The potential of circuit point 113 is lowered through transistor 104. The gate of transistor 104 is at circuit point 1
This is common to 15. This circuit point 115 is coupled to a Cc potential source via a depletion mode transistor 106 and to ground via a transistor 107. Since transistors 104 and 105 are relatively large, their internal resistance is lower than that of transistor 101. Assume that a high level signal (5) is present on line 118 to indicate writing a binary 1 to pad 100.

Assuming that a high level signal is applied to line 118 during buffering, that signal will be present on line 118 until a binary O is applied to pad 100. This signal causes transistor 107 to conduct, causing node 105 to go low, thereby causing transistor 110 to become non-conductive. At the beginning of any buffer cycle, the computer's port controller forces the W signal low, so transistor 109 is not conductive during those conditions. Since transistors 109 and 110 are not conductive, circuit point 114 is pulled up to Cc via transistor 108. Therefore, transistor 105 becomes conductive and charges circuit point 113. When the φ signal becomes positive again, node 114 is pulled down to ground potential through transistor 109, so that transistor 105 becomes non-conductive. However, circuit point 113 is transistor 1
01 to maintain the Vcc potential. As mentioned above,
Since the internal resistance of transistor 105 is relatively low, the potential at output circuit point 113 is quickly pulled up to Vcc.
Therefore, this output port functions as a true high level fixed output terminal or a pull-up resistor for an external device. This provides great flexibility for coupling the computer to external circuitry. line 11
When a binary O, that is, a low level signal is applied to 8, the transistor 107 does not become conductive, so the circuit point 1
15 is kept at Vcc potential by a depletion load. Transistor 104 is therefore rendered conductive, pulling circuit point 113 towards ground potential. Since the circuit point 115 is at Cc potential, the transistor 110
becomes conductive and prevents pull-up transistor 105 from becoming conductive. Binary 1 is circuit point 113
has already been written in pad 100, and pad 100
Assume that a binary O is added from outside vc.

At this time, since the node 113 is at the Cc potential, the transistor 102 is in a conductive state and the line 119 is in a conductive state.
It should be noted that this is grounded. For example, T.T.
When a binary O is applied to pad 100 through the L circuit, point 113 quickly discharges because the external circuitry can easily override the small sustaining current flowing through transistor 101. Depletion mode transistor 103 then pulls line 119 to the Cc potential to provide the appropriate signal on line 119. If data is to be received from an external data source at the beginning of each buffer cycle, line 118 is pulled high by the port controller. To this end, if pad 100 has previously been fixed to ground potential by transistor 104, a binary 1 can now be applied to pad 100 externally. Next, refer to FIG.

A single column decoder is shown in this figure, which is coupled to the programming circuitry by line 141. A plurality of such column decoders are used, each column decoder coupled to the programming circuit shown in FIG. For example, other column decoders are coupled to the gates of column select transistors 148. This programming circuit is line 13
Programming pulse (PROG) applied via
is applied to the selected column through a column select transistor, such as transistor 147 or 148. Column decoder transistors 123a-123d are coupled between node 126 and ground.

The gates of these transistors are coupled to receive an input address in the conventional manner. When the decoder shown in FIG. 6 is selected, transistors 123a to 123d do not become conductive. Circuit point 1
26 is coupled to a VDD potential source via depletion mode transistor 128. The gate of transistor 128 is also coupled to node 126. The circuit point 126 is coupled to the Wcc potential source through a depletion mode transistor 131, the gate of which is connected to the PR
G signal source. In the programming circuit, the programming pulse (line 13) is connected to transistor 14.
4 to circuit point 150 (transistors 147, 148
drain).

The gate of transistor 144 is coupled to line 13 through bootstrap capacitor 142 and also to node 138 through transistor 140.
This circuit point 138 is coupled to the VDD potential source via a pull-up transistor 134. The gate of transistor 134 is coupled to the PRG signal source via inverter 132. Parallel pulldown transistors 135 and 136 are grounded at node 138. A data input signal is applied to the gate of transistor 135, and the gate of transistor 136 is coupled to receive the PRG signal. During the programming mode, the potential VDD is raised to about 25.

This potential rise is detected by a circuit such as that shown in FIG. 4, when the human power line 19 is coupled to the DD potential source. The output from this detection circuit is used to generate the PRG signal. During programming, line 13
The 20v pulse applied to the column must be sent to the column line through the column select transistor and to the drain of the selected transistor.

Body effects (BOd) specific to the embodiment described here
errect), the gate potential of the column select transistor must be approximately 2 to send this programming pulse.
Must be raised to 5. This potential is applied to depletion mode transistor 1 when the decoder is selected.
Obtained from 28. During programming, node 138 is coupled to the DD potential source through transistor 134.

During programming, the inverter output is approximately equal to VDD. When the data input signal is low level, circuit point 138
remains charged. When a programming pulse is applied, the gate of transistor 144 is controlled by bootstrap circuitry to provide the overall magnitude of the pulse to circuit 150. Transistor 140 causes the gate potential of transistor 144 to rise above VDD, thereby preventing breakdown of the transistor. When a binary 1 is applied to transistor 135, circuit point 138 and the gate of transistor 144 are at approximately ground potential, thereby causing a positive pulse from line 13 to circuit point 1.
Prevent it from being sent to 50. When the positive pulse on line 13 is applied to the column line, the selected PROM
Charge is injected into the floating gate of the cell3.

This will cause the cell to have a higher threshold potential than the n-channel cell being employed. In the row decoder shown in FIG. 7, node 159 is grounded through a plurality of row decoder transistors 154a-154f and coupled to word line selection transistors.

Similarly, other transistors are also coupled to other word line select transistors. These transistors are used to ground the selected word line (the source terminal of the cell) to the programming terminal. Node 159 is coupled to a Vcc potential source through a depletion mode transistor 157, the gate of which is coupled to a PRG signal source. Node 159 is also coupled to a VDD potential source via depletion mode transistor 156. Transistor 153 grounds node 159 to discharge node 159 and prevent the word line from being prematurely selected. During reading (not programming), line 159 is connected to depletion mode transistor 15 unless decoding transistors 154a-154f are all conducting.
7 to become VOc.

During programming, transistor 157 is not conducting, so node 159 is disconnected from the CO potential source. When DD rises to 25V, transistor 154a
If ~154f is not conductive, circuit point 159 is pulled up to that potential. A decoder is selected under such conditions. Since the time required to discharge node 159 during programming is not critical, the internal resistance of transistor 156 can be relatively high. The digital computer that can be completely incorporated into one board has been described above.

This board contains a CPU, RAM used to store data within the computer, and PRO, which can be erased and reprogrammed and is used to store computer programs.
M is included.

[Brief explanation of drawings]

Figure 1 shows the main parts of the CPU, RAM, and PROM.
FIG. 2 is an overall block diagram of the computer of the present invention showing
The figure shows a detailed block diagram of a logic circuit with a program counter used for testing PROM, RAM and CPU, and for addressing external storage devices. FIG. 3 shows how to select a RAM address. A block diagram of the logic device and circuit; FIG. 4 is a block diagram of the third state level detector used in this computer;
Figure 5 is a schematic diagram of the buffer used for the computer's "pseudo" bidirectional data lines; Figure 6 is a schematic diagram of the column decoder and programming circuitry used to program the PROM; Figure 7 is a schematic diagram of the row decoder. It is. 12...PROMll4...RAMl
l6... CPUl2O... Board, 27
・・・・・・Program counter, 29, 31, 70・
... Switching device, 33 ... Third state level detector, 37 ... Instruction register, 39
...Instruction decoder, 72 ...Stack pointer register, 74 ...Multiplexer,
76...RAM address register.

Claims (1)

[Claims] 1. A bidirectional data bus having terminals for connection to an external circuit device, and a random data bus coupled to this data bus.
a central processing unit coupled to the data bus and the random access memory for performing computational functions and controlling operation of the computer;
A MOS digital computer in which the central processing unit, a read-only memory coupled to the data bus for storing program bytes, and an input detection device are formed on a single silicon substrate, The central processing unit includes a program counter coupled to the read-only memory and a data bus, and provides an address signal to the read-only memory when the program counter indicates a value less than or equal to a predetermined count value; When the program counter indicates a value equal to or greater than the predetermined count value, an address signal is provided to the external storage device, and the input detection device receives the predetermined signal and provides a control signal to the program counter and the read-only memory. and supplying a command from the external storage device to the data bus irrespective of the count value of the program counter when the first predetermined signal is received by the input detection device, and the second predetermined signal The read-only memory is coupled to a data bus so that programs stored in the read-only memory can be examined when received by an input sensing device, thereby reducing the program storage capacity of the computer. A MOS digital computer, characterized in that it is expandable by the use of an external storage device that is automatically addressed by signals from a program counter, and that the read-only memory and the central processing unit can be tested separately. 2. The computer according to claim 1, wherein the read-only memory is a programmable read-only memory. 3. The computer of claim 1, wherein the predetermined count is approximately equal to the maximum number of bytes that can be stored in the read-only memory. 4. The computer according to claim 3, wherein the input detection device is a voltage level detection device that detects three logic states on a single line. 5. A computer according to claim 1, wherein the computer is assembled with n-channel equipment. 6. The computer of claim 5, wherein the n-channel device includes a polysilicon gate. 7 a data bus, a read-only memory coupled to said data bus for storing program bytes, and a program coupled to said read-only memory and said data bus for addressing said read-only memory; a counter; and a central processing unit coupled to the data bus, including an arithmetic logic unit for performing arithmetic operations, for interpreting and executing instructions from the read-only memory; A MOS digital computer having a random access memory coupled to the random access memory and a random access memory for storing digital signals formed on one substrate, the computer comprising a random access memory coupled to the random access memory and a random access memory for storing digital signals.
a memory address register, the random access memory address register receiving an input address from a multiplexer, the multiplexer being coupled to select a first address bus or a second address bus, the first address bus being connected to the first address bus; coupled to receive from the data bus an address corresponding to a location in the random access memory and selectively applying a predetermined signal to the first address bus to select a location in the random access memory; the second address bus is coupled to a stack pointer register to provide an address signal indicating a location in the random access memory for storing the contents of the program counter; The stack pointer register automatically increases or decreases an address signal indicating a location in the random access memory according to the contents of the program counter, and the computer stores information in the random access memory. a third address bus coupled to said multiplexer and said random access memory so that said address can be used to select a location within said random access memory; The directly addressable location in the random access memory may be addressable at the time the circuit arrangement is storing data elsewhere and the directly addressable location in the random access memory is storing data. MOS digital computer, and wherein said random access memory is used to store the contents of said program counter along with said stack pointer register automatically providing an address signal. 8. The computer of claim 7, wherein the read-only memory is a programmable fixed storage device. 9. The computer of claim 7, wherein said circuit arrangement is a bistable circuit providing said location, said bistable circuit coupled to said first address bus. 10. A computer according to claim 9, wherein the stack pointer register has means for adding a binary 1 to the address of the second address bus, thereby causing the contents of the program counter to be randomly accessed. A computer that allows data to be stored in contiguous locations in memory. 11. The computer according to claim 10, wherein said random access memory comprises static random access memory. 12. A computer according to claim 10, wherein the computer is assembled with n-channel equipment. 13. The computer of claim 12, wherein the n-channel device includes a polysilicon gate.