JPS5931595A - Signal transmission system for digital dimmer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION As shown in FIG. 1 of the conventional digital light control device Vi, the +-switch data KSD from the ten-matrix circuit +11 of the operating section A, that is, the data indicating which Only the parallel serial data is converted into serial data SD by the conversion circuit +21 and sent to the dimming control unit B.
In the dimming control section B, the serial data SD sent by the serial/parallel conversion circuit (3) is converted into parallel data PD.
, and the phase control circuit (41 is this parallel data P
From D, it is determined which digit on the operating section A is pressed, and corresponding to that digit, a 0 column is set in advance and a certain signal processing operation is performed to create a dimming tie three-digit signal PS. Dimming circuit +51 VC is output to perform predetermined dimming.

By the way, the phase control circuit +41 is composed of a low-voltage digital circuit that is prone to malfunction even with low noise. There was a risk of malfunction due to switching noise of a phase control element such as a thyristor used, and since it was sensitive to heat, there was also a risk of damage to the phase control element performing power control 1 due to heat.

The present invention has been made in view of these drawbacks, and its purpose is to provide most of the phase control circuit, which is composed of digital circuits, in the operating section to eliminate noise sources and the dimmer circuit, which is a heat source. An object of the present invention is to provide a highly reliable transmission method for a digital light control device that eliminates shadows caused by shadows.

The present invention will be explained below with reference to Examples. FIG. 2 shows an overall circuit block diagram of one embodiment, in which the operation unit AKd and the matrix circuit Il+ and the matrix circuit Il+ determine the data KSDi. , a phase control circuit 14'' that creates all the dimming data corresponding to the + and -, and creates parallel dimming tie three signal P'S corresponding to each dimming circuit based on the dimming data. A parallel/serial conversion circuit 12) is provided, and a dimming signal PS converted into serial data is sent to the dimming side part a B via a transmission line t. The dimming control unit B includes a serial-to-parallel conversion circuit f31 that converts the dimming tie three signal PS sent from the operating unit A as serial data into parallel data, and the dimming tie three signal converted to parallel data. Based on the signal, the lighting load (
(not shown).

FIG. 3 shows a specific circuit of one embodiment, in which the phase control circuit 14) is connected to the microphone 0 processor (hereinafter abbreviated as CPU) (
6), a read-only ROM +71 that stores 6 pieces of data in advance, a RAM +81 that stores and reads out data such as dimming data, and a timer (11), 02 ), etc., and perform one operation as follows. In other words, in Figure 5, when the power supply (91 is turned on and the device starts), the CPU 161 first uses the built-in ROM +7+ and the RAM +81. At the same time as clearing the memory contents and performing initial settings (■), internal processing (■) such as 10-S + YAN is performed, and the RAM is cleared.
Each dimming circuit (5,) is selectively set to a predetermined address of 181 based on data from the +-7 trix circuit Ill.

Set the dimming data Mill, . . . In addition, CPU1#l is connected to the AC power source shown in Figure 4 (at).
A power supply circuit 110 generates power in response to the zero cross of
The falling edge of the power synchronization signal (shown in Figure 4 (bl K)) of 1 is detected by the Stellar 2 in Figure 5, and the phase control processing operation 2 is performed. 0-chit t2- of the circuit (processing operation of 41') is shown. First, when the falling edge of the power synchronization signal described above is detected, the digital dimming is secured in a predetermined area of RAM+81. At the same time as setting the contents of the variable Fl indicating which stage of dimming circuit 1 to "1",
The contents of variable F2 indicating whether the process is 51 are set to "1". In other words, steps ① and ② of the flowchart are completed.

This process is carried out by the first dimming circuit (5I) of the first stage, that is, F
l=1. F2. = 1, the second dimmer circuit in the first stage (5,), ... the m-th dimmer circuit in the first stage (
5m), the first dimming circuit (51) in the second stage, and so on up to the mth dimming circuit (5m) in the nth stage. In the embodiment, for example, the number n of dimming stages is 5, and the number m of dimming circuits is (51) to (5,).

When the above-mentioned setting of F1=1 and F2=1 is completed, the first timer I
Activate IJ. This first timer:ll is used to set a half cycle of the commercial same wave according to the dimming stage. Now, the operation of the first timer 111) is started.In the cleverness of Stella, "1" is added to the content of the corresponding dimming data MIIJ stored in RAM +81 in the first dimming circuit (5+)K, and the dimming is started. The content of optical data M111 is the number of stages n
It is determined in step (3) whether or not it is equal to . For example, if the initial content of the dimming data M (11) is "3", then M (F2) = = n (however, n = 5) does not hold, so it jumps to Stella zu 0 and changes the variable F2. IIJ in the content
Add. In other words, the process shifts to the second circuit. Now, after completing step ①, in step 0, it is determined whether or not the judgment of dimming data of all circuits has been completed, and F2
=m+1 (however, m-5) holds true1. , 'z Keh Return to step■. Now, the second dimmer circuit (52) K
Assuming that the content of the corresponding dimming data M12) is "4", when "1" is added in step (2), the determination formula M(F2)=H in step (2) is established. In other words, the second dimming circuit (52) Vi is set to the second stage dimming #. Now, moving from step (2) to (2), the human data output terminal PI21 corresponding to the CPIJf61Vi dimming circuit (52) is set to 'H' L/bevel. At the same time, the second timer (ratio is started at step 2) and the 1H level output period of the f-tater output terminal P12 is controlled by the output period of the second timer 12+. 1st timer 11!)
It operates for a period of time that divides the section corresponding to the operation period of 17m into 17m. Now, in step ■, the second timer α
When the CPU 161 detects the time-up of 2, the CPU 161 changes the lH# level output of the data output terminal P12 to 1 (, level) as shown in FIG.
Then, the process moves on to the determination of the next circuit's dimmer meter M (F2). In this way, the first stage dimming circuit (5
When the judgment of the dimming data M (F2) of I) to (5b) is completed, it is judged in step O whether the operation of the first timer 111) has stopped, and if it has stopped, the inverse number F
1 is added to the contents of l, and the next step is also set to 0 to determine whether the total number of stages n has been completed. If not, the process returns to step (5])～
The determination of the dimming data M (F2) in (52) is performed sequentially in the same way as in the case of the first stage. JAI, the first in Japan
Assuming that the dimming data MHI of the optical circuit (5,) is "3" at the time of initial setting, the number of judgments in the first stage is Stella
Since "1" has been added to the data and it has become "4", the decision in Stellar 2 is 1-1 YES. Therefore,
As shown in tel in Fig. 4, the operation period in Fig. 4 (first timer 1!1 corresponding to the second stage of the dimming stage of cl) is set to 1/rrL.
In the first divided period 1..., the CPU 161 sets the output of the data output terminal Ptit to IH rube), and
During the operation period of the corresponding second timer l1 shown in Figure (di), the 'H level 1ktl is maintained.In this way, each dimming circuit (
The dimming data M111 to M15) of 51) to (55) are determined, and the dimming circuits (5]) to (
5) during the period allocated to the dimming data M111 to M
15), CPU +61 has each dimming circuit (51)
~(5g) (C corresponding data output terminal P ill
~P(61 outputs a signal.

In other words, during a half cycle of the power supply frequency, based on the power supply synchronization signal, the entire dimming circuit is set at equal intervals corresponding to the number of dimming stages. 16) Therefore, the second timer 021 is used to divide each divided period into each dimmer circuit 1.
61, and CPU I61 is the data output terminal P.
From ill..., the tie-interceptor that outputs the Il(Level signal) is the tie-interconnect for the phase control power of the optical circuit (51)..., that is, the dimming tie:,7 When outputted from the data output terminal P (11...), the signal is made into a dimming tie signal.Now, the signal outputted from the data output terminal P111... of the CPU161 is outputted via the OR gate (131). Therefore, the signal output from the OR gate (1□□□ becomes a serial signal as shown in Figure 4 (fl).
A parallel/serial conversion circuit 12) is configured to convert the parallel signal outputted from the data output terminal P111 of P U +61 into a serial 1 signal. Now, this serial signal is sent to the dimming control section B via the transmission line t.

The dimming control unit B is a demultiplexer f141. Kalinta 0
6), a serial-to-parallel conversion circuit (3) consisting of a pulse generator 0611 power supply synchronization circuit (22), etc., and a series circuit of a triac U91 and four lighting loads connected to an AC power supply. It is composed of an optical circuit (5)... The pulse generator (I6) synchronizes the operation time of the second timer 1I21 as shown in FIG. The count output, which is the BCD code, is sent to the dimming circuit (5
s)..., and the demultiplexer 11
41H counter (based on the address data input from 151, the corresponding data output terminals CILL, CI
21... It is designed to generate more output. Also, when the counter (16) counts "5", the VC
The output of the acid gate 211 is set to '11', and it is reset by the IHL level signal through the OR gate (231), and the synchronization signal of the power supply synchronization circuit (zero D
VC so that it can also be reset by a signal corresponding to
It has become. Then, the input serial signal is sent to a demultiplexer (I41 branches and outputs it sequentially from data output terminals Cm, C121, . . . based on address data, and these data output terminals Cill, C121, . . .
The respective triacs 09) of the respective dimming circuits (51) connected correspondingly to the data output terminals CIll,
The ignition is made conductive at the timing of the signal from CI21... @Figure 4 (if f counter (I5)
The counter value of UIVi data output terminal C11 in FIG.
1 and the voltage waveform of FIG. 4 (kl is triac α9 of the dimming circuit (51)). In other words, as can be seen from these figures, the data output terminal P of CPUf61
A signal synchronized with the dimming tie signal output from Ill... is regenerated from the demultiplexer (I41) as a gate signal of the triac 09)... of the corresponding dimming circuit (51)... , and the operation section AV
The feature is that a dimming timing signal is created during the interview in C. When the processing of all stages in a half cycle of the commercial frequency is completed, the process exits from step 0 of the flowchart of FIG. 6 and waits for the next half cycle of the commercial frequency.

In addition, the contents of each dimming data M Ill... before the processing operation by 0-chisate in FIG. The set dimming level is verified by determining whether or not the value matches the total number of levels. Also, in FIG. 3 (181ViCP U+6+ is an oscillation section for glue D-sock).

As mentioned above, a half cycle of the commercial frequency is divided chronologically according to the number of dimming stages, and a
M dimmer circuit [one-to-one corresponding periods are set in chronological order, and the dimmer tie three pass signal is adjusted during the period corresponding to the selected dimmer stage and dimmer circuit. A phase control circuit that outputs each optical circuit separately is provided in the operating section, and the parallel output of the phase braking circuit is transmitted to the dimming control section via the transmission line as a dimming die three-digit pulse signal and all serial data. The phase control circuit, which is a digital circuit, can be separated from the dimming control section, which is equipped with a dimming circuit, as in the past, so the digital circuit in the dimming control section can be minimized, and the dimming circuit The switching noise of the phase control element and the effects of heat generation are reduced, so there is less risk of malfunction or damage, and the reliability is also improved by m1.

[Brief explanation of drawings]

Fig. 1 is a diagram of a conventional circuit, Fig. 2 is a schematic circuit and lock diagram of an uninvented embodiment of Q, and Fig. 3 is a concrete circuit diagram of the same as above. al ~ (10 is the same as above time chi t'-1-1% 5 and 6 are flowcharts for explaining the same operation, A is the operating section, B is the dimming control section, t is the transmission line, 12 ) is a parallel/serial f conversion circuit, (3) is a serial/parallel conversion circuit, )4)'
is a phase control circuit, (5□), , u dimming circuit, (I9)
is the triac, and COI is the lighting load. Agent Patent Attorney Ishi 1) Chief 7@5E 2■ Ri■ ) 1/' J■ ] ] 〉 ]

Claims (1)

[Claims] Ill The half cycle of the commercial 1D wave is divided chronologically according to the number of dimming stages, and the period corresponding one-to-one to the installed dimmer circuit is set chronologically in each divided section. A phase control circuit is provided in the operating section to output a dimmer tie three-pulse signal for each dimmer circuit separately in the period 1 m corresponding to the dimmer stage and the dimmer circuit, and
The parallel dimmer tie three pulse signal is transmitted as serial data to the dimmer control unit via the transmission line, and the serial data is transmitted to the dimmer tie three pulse signal corresponding to each different dimmer circuit. A serial/parallel conversion means is provided to convert the reproduced dimming tie signal into a signal.