JPS5931148B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data processing device, in particular, a data processing device, in which logical page addresses corresponding to a plurality of operands are each held as a physical page address, and the above-mentioned holding is performed as long as a page fault or the like does not occur. In a data processing device that is configured to access using physical page addresses that have been assigned, if a page fault occurs in response to one of the operands, the physical page address corresponding to the other operand will be accessed. The present invention relates to a data processing device which issues an invalidation instruction and performs flexible address conversion when the other operand is actually accessed.

In relatively small-scale data processing equipment, physical page addresses are held for multiple operands that are considered to be actually processed in order to save address translation time, and page faults do not occur. For a limited time, access is performed using the held physical page address. In this type of method, when a page fault occurs in response to one of the operands, the address translation mechanism extracts the physical page address corresponding to that operand. As shown in the flowchart shown in FIG. 1, the address translation mechanism is indexed by logical addresses corresponding to other operands. That is, the physical address corresponding to each other operand is re-extracted to ensure that the physical page address held for each of the other operands is valid. However, depending on the processing mode, the physical address that has been extracted in advance may not actually be used, and in such a case, address translation is performed in vain. This is especially wasteful in small-scale data processing devices where the time required for address translation processing by an address translation mechanism such as a TLB index cannot be ignored. The present invention aims to solve the above points, and the data processing device of the present invention extracts the respective physical page addresses corresponding to the logical page addresses of a plurality of given logical addresses, and held in the page address register and extracts the physical page address by the address translation mechanism when a logical page boundary is crossed after a logical address update and/or when accessed by a newly generated logical address In the data processing device, the address translation mechanism performs address translation on any one of the plurality of logical addresses, and when a page fault occurs, the physical page address corresponding to the other logical address is The present invention is configured so that an address conversion instruction flag is set for the logical address, and the address conversion mechanism is forced to perform address conversion when an access request is made to any of the other logical addresses. It is a feature. This will be explained below with reference to the drawings. Second
The figure is a flowchart of an embodiment explaining the operation of the present invention.
FIG. 3 shows the configuration of an embodiment of the present invention.

In the case of the conventional power type, as shown in the illustrated flowchart in FIG. It goes without saying that the physical page address RA/ is correspondingly extracted, but at the same time, the logical addresses LB and LC corresponding to other operands are also corresponding to each other using an address translation mechanism (TLB index, etc.). The physical page addresses RB and RC are extracted again and retained.

In contrast to the above, in the case of the present invention, the following is done for the reasons stated at the beginning of this specification.

That is, as shown in FIG. 2, for example, when a page fault occurs with respect to the logical address LA, it goes without saying that the physical page address RA' is extracted in correspondence with the new logical address LN, but at this time, other operands are Physical page addresses RB and RC held correspondingly
The address conversion instruction flags XB and XC should only be turned on. In other words, the physical page address RB or RC is merely an indication that it is invalid. Address translation is then performed only when an access corresponding to the other operand actually occurs. FIG. 3 shows an embodiment of the invention.

Symbols 1A, 1B, and 1C in the figure represent operands A, B, and
A logical address register corresponding to C, 2 an address translation mechanism, and 3A, 3B, and 3C physical page address registers for logical page addresses LA, LB, and LC corresponding to operands A, B, and C, respectively. Physical page addresses RA, RB, RC are set and held; 4 is a microinstruction read from a control memory (not shown); SRQ is memory access request information; 5 is a decoder; XA, XB, XC is an address conversion instruction flag corresponding to each physical page address, 6
1 is a write logic section that diagrammatically represents the write logic by software for address conversion instruction flag XA, etc.; 7, 8, and 9 are AND circuits; 10 is an OR circuit; 11
represents or logic. Logical addresses corresponding to a plurality of operands are set in the husband registers 1A, 1B, 1C, and when the logical addresses are newly generated and set, the address translation mechanism 2 converts the respective logical page addresses LA, LB, Physical page addresses RA, RB, and RC corresponding to LC are extracted and stored in registers 3A and 3.
It is set to B, 3C.

Each physical page address RA, RB, RC is in register 3
A, 3B, and 3C respectively, and the microinstruction 4
When an access corresponding to, for example, logical address register 1A is performed by , physical page address RA is read out and register 1
The in-page address in A is read and used as a memory access address to access memory. Therefore, the contents of the logical address register 1A are updated by +1 or +2 (at this time, the contents of the other logical address registers 1B and 1C are also updated at the page boundary by a page checker (not shown). If the page boundary is exceeded, a flag XA is set for the contents of register 3A via illustrated OR logic 11, and the When the original access is performed, the AND circuit 7 is turned on and a page cross occurrence interrupt occurs.That is, the logical address register 1
The address translation mechanism 2 is accessed using the logical page address LA in the contents of A, and the newly extracted physical page address RA is set in the register 3A. Then, the memory is accessed using the physical page address RA and the intra-page address in the register 1A. For operands that have actually crossed the page boundary, in other words, caused page clutter, address translation is performed as described above. At this time, if there is no physical page corresponding to the logical address LA on the main memory, that is, the page
When in a fault state, the contents of physical page addresses RB and RC of logical pages LB and LC corresponding to other operands are no longer guaranteed, so address translation must be performed. In the present invention, in response to a page fault occurring with respect to logical page address LA, the microprogram only sets flags XB (5XC), respectively, and in page fault processing for LA, LB , LC is not performed. Then, when access based on the contents of logical address registers 1B and 1C is actually performed by microinstruction 4, AND circuits 8 and 9 are turned on, It is forcibly made to assume that a page cross has occurred. That is, for example, when an access based on the contents of register 1C is actually performed, AND circuit 9 is turned on and physical page address RC is extracted. As explained above, according to the present invention, even though a new physical page address has been extracted, it is no longer completely unused, and address translation is performed only when an actual access is performed. It will be.

As explained with reference to FIG. 3, the address conversion instruction flags XA, If the flag set by 1 is made common with the flag that indicates that a page cross has occurred in the operand corresponding to the contents of register 1A (for example, in the contents of register 3A), the flag set by Since the flag writing means and the like are already existing, it has the advantage of not requiring any changes in hardware.

[Brief explanation of the drawing]

FIG. 1 is a flow chart illustrating the operation of a conventional method, FIG. 2 is a flow chart of an embodiment illustrating the operation of the present invention, and FIG. 3 is a diagram showing the configuration of an embodiment of the present invention. In the figure, 1A, 1B, and 1C are logical address registers, 2 is an address translation mechanism, 3A, 3B, and 3C are physical page address registers, 4 is a microinstruction, 5 is a decoder, 6 is a write unit, and XA , XB, and XC represent address conversion instruction flags, respectively.

Claims (1)

[Claims] 1 The result of extracting each physical page address corresponding to the logical page address of multiple given logical addresses is held in the physical page address register, and when the logical page boundary is exceeded after the logical address is updated. and/or in a data processing device adapted to extract a physical page address by an address translation mechanism when accessed by a newly generated logical address, the address at any one of the plurality of logical addresses; When address translation is performed by the translation mechanism and a page fault occurs, an address translation instruction flag is set for the physical page address corresponding to another logical address, and any of the other logical addresses is A data processing device characterized in that the address conversion mechanism forcibly performs address conversion at the time when an access request is made to the data processing device.