JPS5930972B2 - Air conditioner control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay control circuit for starting an air conditioner compressor.

Conventionally, the blank fan and compressor of an air conditioner repeatedly start and stop at the same time depending on whether the operation is turned on or off.

However, when not only the indoor fan and compressor of the air conditioner, but also all other home appliances in the home are started at the same time, such as when recovering from a power outage, the total starting current becomes excessive. There were some inconveniences such as the breaker tripping.

In such cases, the startup timing of the air conditioner compressor, which requires a relatively large starting current for a home appliance, may be slightly delayed (by a few seconds) and the compressor may be started after the starting current of other home appliances has decreased. By doing so, the above-mentioned inconveniences can be prevented, and therefore, a delay control circuit for starting the compressor upon resumption of operation using an electronic control circuit as shown in FIG. 1 has heretofore been used.

In the same figure, 1, 2, 3 are frequency dividers, 4 is an inversion gate,
5 is an R-S flip-flop.

Also, a is a reference time signal, b is an initial state setting signal, C is an operation start signal, d is a frequency division pulse, e is an inverted signal of signal C,
f is a division pulse, g is a signal for starting the compressor with a delay (hereinafter referred to as compressor delay output), and h is a division pulse to the next stage.

FIG. 2 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 1.

Now, this circuit is energized, and the initial state setting signal has already completed the resetting of the branch unit that is necessary at startup.
Consider the state in which the signal is turned off.

A reference time signal a is applied to a divider 1, and its frequency-divided pulse d is applied to frequency dividers 2 and 3.

When the operation start signal C is turned on, the resetting of the branch unit 3 is canceled and counting starts, and after a predetermined delay time t has elapsed as shown in FIG. 2, the branch pulse f starts to be output. The compressor delay output g is turned on, and the compressor is started with a delay of time t after the operation start signal C is turned on.

Note that the delay time t varies somewhat depending on the output timing of the branch pulse d (determined in relation to the reference time signal a) and the time when the operation start signal C (independent of the signals a and d) turns on.

In the circuit shown in Fig. 1, the frequency divider 3 is reset and stops operating while the operation start signal C is off, so even if it is necessary to perform other time control, the frequency divider 3 is not activated. Not available.

However, in order to control the operation of the air conditioner compressor, in addition to this delay control circuit to reduce the starting current, there is also a compressor lock prevention circuit (which prevents the compressor from restarting within about 3 minutes after stopping).
In some cases, a sleep timer circuit (which operates after several hours) is required, and in such cases, if the conventional delay control circuit shown in Figure 1 is used, a separate delay divider will be required. .

Therefore, the circuit size increases, and even when integrated circuits are integrated, the chip size increases and the cost increases.

The present invention eliminates the drawbacks of the conventional control circuit, and provides an air conditioner control circuit in which a delay control circuit for reducing starting current and another time control circuit share a branch unit, and which requires a relatively small-scale configuration. The purpose is to provide.

In order to achieve the above object, the present invention generates a signal that is connected to a predetermined divider in a multi-stage frequency divider that divides a reference time signal and resets this frequency divider according to an initial state setting signal. In addition, there is a set/reset circuit (actually an R/S flip-flop) that generates a signal to set this branch unit in response to the air conditioner operation start signal, and a signal that closes the air conditioner compressor drive motor circuit. a control circuit that uses the output signal of the predetermined branch unit to generate a delayed output signal (actually, this is also an R-S flip-flop) that generates a delay output signal after a predetermined time delay from the input of the air conditioner operation start signal. The branch unit whose reset has been released is used not only as a start-up delay control circuit for the compressor drive motor but also in other time control circuits.

FIG. 3 is a diagram showing one embodiment of the present invention.

In the figure, 11 and 12 are frequency dividers, 14 is an inversion gate,
15°16 is an R-S flip-flop.

e' is the inverted signal of the operation start signal C, g' is the compressor delay output, h' is the branch pulse to the next stage, i is the reset signal,
a j b I e and d are the same as in FIGS. 1 and 2.

FIG. 4 is a signal waveform diagram for explaining the operation of this embodiment.

The divider 11 of the circuit of this embodiment corresponds to the divider 1 of the conventional control circuit shown in FIG. 1, and the divider 12 also functions as dividers 2 and 3 of the circuit shown in FIG. It is.

When the initial state setting signal S is input, the frequency divider 11 is immediately reset, and the R.S. The output i of the knob resets the branch unit 12.

Since the initial state setting signal S is once turned on and then turned off soon, the reset state of the divider 11 is also released at the same time, and the divider 11 supplies the divided pulse d of the reference time signal a to the frequency divider 12.

However, the R-S flip-flop 16 continues to send the frequency divider 12 heliset signal i even after the signal is turned off, so the divider 12 does not operate at this stage.

When the operation start signal C is sent, the R-S flip-flop 16 is reset, the reset signal j is no longer sent to the branch unit 12, and the branch unit 12 operates and starts counting.

As a result, the division pulse h' to the next stage, which is obtained by further frequency-dividing the division pulse d, is output with a delay of a predetermined time t from the time when the operation start signal C is turned on.

Reversing gate 1 until the other operation start signal C is sent.
The R-S control flop 15 (delayed output signal generation circuit) is held in a reset state by the output e' of 4, and the signal C is sent, and the reset signal input to the flip 70 block 15 is eliminated. Noritsubu flop 1 after
5 remains in the reset state due to its inherent nature.

However, as mentioned above, when the output frequency division pulse h' of the divider 12 is input to the flip-flop 15 after a predetermined time t delay from when the signal C is turned on, the reset signal of the divider flop has already been input. Since it is off, the flip 70 knob 15 is immediately set, and its output, that is, the compressor delay output g', is turned on and the compressor drive motor circuit is closed.

When the operation start signal C is turned off, the reset signal e' to the R-87 lip-flop 15 is turned on and this state is maintained, so that the compressor delay output g' is turned off and the compressor is stopped.

However, even if the signal C is turned on or off, the branch divider 12 is not reset and continues to send out the branch pulse h' unless the initial state setting signal S is input.

Note that in the conventional control circuit shown in FIG. 1, the compressor delay output g is always turned on after a predetermined time t delay from the operation start signal C, whereas in the circuit of this embodiment, the initial state setting signal Suga is input. Output g' is always turned on with a delay of time t from signal C only the first time after signal C is turned on, but after that, output g'
' may turn on at the same time as the signal.

However, excessive starting current becomes a problem only when recovering from a power outage, in which case the initial state setting signal is always input, and the output g' is always turned on after a predetermined time delay from the signal C, so there is no problem. do not have.

As explained above, according to the present invention, the operation of three branchers, which were required separately in conventional circuits, can be reduced to one operation without deteriorating the control characteristics that suppress excessive starting current upon recovery from a power outage. This makes it possible for the branch unit 2 (
(depending on time accuracy requirements, 2 to 4 stages of flip-flops are usually required), the circuit configuration can be made smaller, making it easier to integrate into an integrated circuit, and reducing costs. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional electronically controlled compressor start-up delay control circuit, FIG. 2 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a diagram of an embodiment of the present invention. , FIG. 4 is a signal waveform diagram for explaining the operation of the embodiment circuit shown in FIG. 3. L2, 3... Frequency divider, 4... Inverting gate, 5... R-S flip-flop, 11, 1
2... Frequency divider, 14... Inversion gate,
15,16...R・S flip-flop, a・
...Reference time signal, b...Initial state setting signal, C...operation start signal sg. g′...Compressor delay output, t...Delay time.

Claims (1)

[Claims] 1. In an air conditioner control circuit that performs multiple time-limited control using a multi-stage splitter that divides the frequency of a reference time signal, it is connected to a predetermined splitter in the multi-stage splitter, and the splitter is set according to an initial state setting signal. A set reset circuit that issues a signal to reset the branch in response to the air conditioner operation start signal, and a signal to close the air conditioner compressor drive motor circuit are connected to the predetermined branch. An air conditioner control circuit comprising: a delayed output signal generating circuit that generates a delayed output signal after a predetermined time delay from the time when the air conditioner operation start signal is input using the output signal of the air conditioner.