JPS593078B2 - Scanning data display and switch status collection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scanning data display and switch status collection circuit.

Conventional monitoring and control panels only had indicator lamps and control switches, and all of their control circuits were provided in the logic control section.

The layout of display lamps, control switches, and switches in the conventional monitoring and control panel is determined for each system based on the user's specifications. Therefore, for the wiring inside the panel, a connection diagram is created for each system and each wire is connected one by one according to the layout, making it impossible to standardize the wiring. In addition, although the circuit configuration inside the monitoring control panel is simple as shown in Figure 1, the more indicator lamps and control switches there are, the more the number of wires increases. Sequence design was required. In Figure 1, is the monitoring panel shown? Each display signal from the logic control section 1 is supplied to each red and green lamp display section RG of the monitoring panel section 2. Here, since the number of wires is two for each display signal of display 1 to display n, the total number of wires is 2 each×n. The present invention solves these problems by connecting the logic control section and the panel section (display (monitoring) panel section, control panel section, control display (or supervisory control) panel section) with a small number of common wiring lines. The purpose of this invention is to provide a scanning type data display and a switch state collection circuit that can reduce the number of data and standardize the data, and will be described below using embodiments. FIG. 2 shows an embodiment of the scanning data display circuit according to the present invention.
1 is a clock oscillation circuit; 12 is a data address counter driven by the clock signal of the clock oscillation circuit 11;
3 is a data bank, and the output MSB (the most significant bit of one data) of the data address counter 12,...
・LSB (least significant bit of one data) is supplied,
A data address is designated by a data address counter 12 to accumulate state changes of a controlled object. Data out signals R (displayed in red) and G (displayed in green) are sent out from this data bank 13 in accordance with the data address designation.
A trigger circuit 14 generates and sends out a memory trigger pulse signal TRG based on the output of the clock oscillation circuit 11.

Also, to describe the configuration of the panel section 2, here the display (monitoring) panel section, the panel section 2 has a plurality of display units 3, and each display unit 3 includes an address setting section 31.
, an address matching circuit 32 for detecting an address match between the address setting signal of the address setting section 31 and the data address signal MSB, . . . , LSB from the data address counter 12, and this address matching circuit 3.
It has a display section that stores and displays each data out signal from the data bank 13 under the AND condition of the address match signal of No. 2 and the memory trigger signal from the trigger circuit 14. Describing the configuration of the display section 33, 41 is an AND circuit to which the address match signal of the address match circuit 32 and the memory trigger pulse from the trigger circuit 14 are supplied, and 42 and 43 are each supplied with the output of the AND circuit 41. , and memory circuits to which data out signals R (red display) and G (green display) are supplied from the data bank 13, respectively; 44 and 45 are driver circuits connected to the output sides of the memory circuits 42 and 43, respectively; 46; , 47 are light emitting diodes driven by driver circuits 44, 45, respectively, and 48, 49 are resistors whose one ends are connected to the light emitting diodes 46, 47, respectively, and whose other ends are commonly connected to the positive power supply P. What? In the monitoring panel section 2? BL is a bus line section for commonly wiring the human output signals of each display unit 3. In the embodiment shown in FIG. In the illustrated embodiment, the bus line section BL is used for common wiring of the human output signals of each control display unit 7. Third
Figures a to g are time charts of Figure 2, and Figure 3 a shows the output (cross signal) of the clock oscillation circuit 11;
B and c in the figure show the LSB and MSB when the output of the data address counter 12 is set to 2 pits (4 addresses), d in the figure shows the output (trigger signal) of the trigger circuit 14, and e in the figure shows the address. The output of the matching circuit 32 (address matching signal) is shown, f shows the output of the data bank 13 (data out signal), and g shows the output of the memory circuit 42.

Based on the scanning data display circuit configured in this way,
In the logic control section 1, the data address counter 12 is driven by 1 using the clock signal (see FIG. 3e) generated by the clock oscillation circuit 11.
A data address is specified in the data bank 13 by the output (see FIG. 3B, c).

The data bank 13 transfers the data contents of the address specified by the address counter 12 to the data out signals R, G (
(see FIG. 3f), the memory circuits 42 and 4 of the panel section 2
3 respectively. On the other hand, the trigger circuit 14 generates a memory trigger pulse j by the clock signal from the clock oscillation circuit 11.
The AND circuit 4 of the display section 33 of each display unit 3 on the panel section 2 (monitoring panel section) side (see Fig. 3 d) is created.
Transfer to 1. On the other hand, in the monitoring panel section 2, an address matching circuit 32 in each display unit 3 detects address matching between the output of the address setting section 31 and the address signal received from the data address counter 12 of the logic control section 1. An AND circuit 41 performs an AND operation between the at Vs match signal of the address match circuit 32 (see FIG. 3e) and the memory trigger signal from the trigger circuit 14, and the output of the AND circuit 41 is used to output the data from the data bank 13. Data of data out signals R and G are transferred to memory circuits 42 and 43, respectively. In this way, the logic control unit 1 sends the data address signal, data out signal} and memory trigger signal to the data address signal line, data out signal line? The data address signal line, the data out signal line, and the trigger signal line that connect the logic control unit 1 and the monitoring panel unit 2 can also be transferred to the monitoring panel section 2 via the connector. The signal line is made common to each display unit 3 of the panel section.

What? Here, as for the number of data addresses, if the address signal is n bits, display scanning of up to 2n addresses is possible.
FIG. 4 shows an embodiment of the scanning switch state collection circuit according to the present invention.
Then, the data address counter 12, the trigger circuit 14, the output SEL from the control section 6 of each control switch unit 5 of the panel section 2, and the output of the trigger circuit 14 are supplied to the data address counter 12. A selection code configuration circuit 15 code-converts the data address signal specified by the data address signal into a selection code and sends the output to a P/S conversion unit, etc., and a selection completion is detected by the output from the S/P conversion unit, etc., and the selection is completed. The selection completion detection circuit 16 sends a signal SO to the panel section 2.

However, the supervisory control panel to which the present invention is applied monitors and controls a plurality of supervisory and control devices, and individual control output circuits (not shown) for these devices are assigned unique selection codes corresponding to the devices. There is. This selection code generally uses a redundant special code to prevent erroneous control, and is provided with an error checking circuit (not shown). Therefore, the selection code corresponding to the 0N signal of the individual control switch recognized by the address designation from the address counter 12 provided in the selection code configuration circuit 15 and the wide logic control unit 1 described above is transferred via a P/S converter or the like. It functions as a code conversion circuit for outputting to the control output individual circuit. Also, to describe the configuration of the panel section 2, here the control panel section, the panel section 2 has a plurality of control switch units 5, each control switch unit 5 having the address setting section 31 and the address matching circuit 32. , the address match signal from the address match circuit 32 and the contact state of the control switch 61 are ANDed in an AND circuit 62, and the AND signal is sent to the selection code configuration circuit 15 and the selection completion detection circuit 16 outputs the AND signal. The control section 6 supplies the output of the AND circuit 63 via the driver circuit 64 to the light emitting diode 65 under the condition that the selection completion signal SO and the contact of the foregoing leg switch 61 are on, and displays the selection completion indication here. There is.

} Regarding the control section 6, 66 is an invar 67, 6
8 is resistance. 5A to 5H are time charts of FIG. 4, FIG. 5A shows the output (clock signal) of the clock oscillation circuit 11, and FIGS. d shows the output (trigger signal) of the trigger circuit 14, e shows the output (address match signal) of the address matching circuit 32, and f shows the output (address match signal) of the address matching circuit 32. The contact state of the control switch 61 is shown in FIG.
The selection output SEL of No. 2 is shown, and h in the figure shows the selection completion signal SO from the selection completion detection circuit 16.

In the scanning switch state collection circuit configured in this way, two
In the logic control section 1, the data address counter 12 is driven by the clock generated by the clock oscillation circuit 11 (see FIG. 5a).
2 (see FIG. 5Bc) is transferred to the selection code configuration circuit 15 and the control panel section 2, where the address designated by the data address counter 12 is code-converted into a selection code. Further, a selection completion signal SO (see FIG. 5h) is transferred from the selection completion detection circuit 16 to the side of the panel section 2. On the other hand, in the control panel section 2, inside each control unit 5}
Then, the address match circuit 32 detects an address match between the address setting signal of the address setting section 31 and the address signal received from the data address counter 12 of the logic control section 1. (see Figure 5 e) and the contact state of the control switch 61 (see Figure 5 f) in an AND circuit 62, and the output (see Figure 5 g) is transferred to the selection code configuration circuit 15. .

Further, when the AND circuit 63 receives a selection completion signal (see FIG. 5h) from the selection completion detection circuit 16 of the logic control section 1, the condition for turning on the contact of the control switch 61 (see FIG. 5f) The output is supplied to the light emitting diode 65 via the driver circuit 64 to indicate selection completion. In this way, the data address signal line and the selection completion signal line connecting the logic control section 1 and the panel section 2, and the signal line from each control section 6 to the selection code configuration circuit 15 are connected to the panel section (corresponding to the control panel section here). This is common to each control switch unit 5 of 2).

FIG. 6 shows an embodiment of the simultaneous scanning data display/switch state collection circuit according to the present invention, and is a combination of FIG. 2 and FIG. 4, and the display of FIG. Part 33
The control section 6 and the control section 6 of FIG. 4 are implemented in the same unit, that is, a control display (monitoring control) unit 7.

In FIG. 6, the logic control section 1 includes a clock oscillation circuit 11, a data address counter 12, and a trigger circuit 1.
In addition, in the panel section (supervisory control panel section) 2, an address setting section 31 and an address matching circuit 32 are commonly used for each control display (supervisory control) unit 7. In this way, the circuits common to FIG. 2 and FIG. 4 can be shared, and the circuit configuration becomes rational. This sixth
The functions of the circuit shown in the figure are the addition of the functions shown in FIGS. 2 and 4, and the time charts thereof are also as shown in FIGS. 3 and 5.

In FIG. 6, a logic control section 1 and a monitoring control panel section 2 are shown.
A data address signal line, a data out signal line, a trigger signal line, a selection completion signal line, and a signal line from each control section 6 to the selection code configuration circuit 15 are common to each control display unit 7 of the panel section 2. This is what I did.

As described above, if the scanning data display and switch status collection circuit according to the present invention is used, the logic control section and the panel section (
The display (monitoring) panel section, control/channel section, control display (monitoring control) panel section) can be connected with a small number of common wiring lines, thereby reducing the number of wiring lines and standardizing them.

For example, to explain the monitoring panel section as an example, the conventional circuit configuration is simple as shown in Fig. Display section RG) It was necessary to design a sequence according to the layout.

On the other hand, in the present invention, the wiring of the monitoring panel section is the same as that shown in Fig. 7, in which all the appliances are wired in the same order for easy connection, regardless of the layout of the appliances (display unit RG (corresponding to 3)). (Display unit RG (corresponding to 3))
If you use a ribbon cable, etc., you can easily accommodate future expansions. Further, in the present invention, the amount of wiring can be significantly reduced compared to the conventional method.

In the present invention, if the number of pits in the address signal is n, then 2
Since n addresses can be scanned, if we use an 8-bit address signal as a comparative example, in the case of the conventional method, the number of devices [monitoring and control units (indicated by 7 in Figure 6)] is 256.
56 (number of appliances) x (2 (R lamp, G lamp) + l (control switch contact)) = 768, but according to Fig. 6 of the present invention, 28 = 256 addresses can be scanned with 8 bits of address, so 8 (Address) + 2 (R lamp, G lamp) + 1 (trigger) + l (with selection) + 1 (selection complete)
= 13 pieces.

(However, as shown in Figure 7, if there is only a monitoring unit, 1
(1 piece)

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the conventional wiring, Fig. 2 is a configuration diagram showing an embodiment of the scanning data display circuit according to the present invention, Fig. 3 is a time chart of Fig. 2, and Fig. 4 is a diagram of the present invention. A fifth block diagram showing an embodiment of the scanning switch state collection circuit according to
The figure is a time chart of FIG. 4, FIG. 6 is a configuration diagram showing an embodiment of the simultaneous scanning data display/switch state collection circuit according to the present invention, and FIG. 7 is a wiring diagram of the present invention.
In the figure, 1 is a logic control section, 2 is a panel section, 3 is a display unit, 5 is a leg switch unit, 6 is a control section, 7 is a control display unit, 11 is a clock oscillation circuit, 12 is a data address counter, and 13 is a 14 is a trigger circuit, 15 is a selection code configuration circuit, 16 is a selection completion detection circuit, 31 is an address setting section, 32 is an address matching circuit, 3
3 is a display section, 41, 62, 63 are AND circuits, 42, 4
3 is a memory circuit, 46, 47, 65 are light emitting diodes,
61 is a control switch, and BL is a bus line section.

Claims (1)

[Claims] 1. Clock oscillation circuit 11 and this clock oscillation circuit 1
1; a trigger circuit 14 that generates and sends out a trigger signal based on the output of the clock oscillation circuit 11; A selection code configuration circuit 15 is supplied with the output and the output of the trigger circuit 14, and converts the specified data address signal from the data address counter 12 into a selection code, and a selection completion circuit 15 sends out a selection completion signal. a logic control section 1 having a detection circuit 16; and an address setting section 31;
and an address matching circuit 32 that detects address matching between the address setting signal of the address setting section 31 and the data address signal from the data address counter 12;
An AND signal of the address match signal from the address match circuit 32 and the contact state of the control switch is sent to the selection code configuration circuit 15, and the selection completion detection circuit 16
a plurality of control switch units 5, each having a selection completion signal from the control switch unit 5 and a control section 6 for displaying selection completion under the condition that the contact of the control switch is turned on; and a bus line for commonly wiring the input and output signals of each control switch unit 5. the data address signal line, the selection completion signal line, and each control section 1 that connects the logic control section 1 and each control switch unit 5 of the panel section 2; A scanning switch state collection circuit characterized in that a signal line from to the selection code configuration circuit is commonly wired via the bus line section BL. 2 Clock oscillation circuit 11 and this clock oscillation circuit 1
a data address counter 12 driven by a clock signal of 1, a data bank 13 whose data address is designated by the output of the data address counter 12 and which accumulates state changes of the monitored control object, and a data bank 13 driven by the output of the clock oscillation circuit 11 A trigger circuit 14 that creates and sends out a trigger signal is supplied with the output from the control section 6 of each control switch unit 5 of the panel section 2 to be described later, and the output of the trigger circuit 14. A logic control unit 1 having a selection code configuration circuit 15 that performs code conversion of a designated data address signal into a selection code, and a selection completion detection circuit 16 that sends out a selection completion signal.
and: an address setting section 31, an address matching circuit 32 for detecting address matching between the address setting signal of the address setting section 31 and the data address signal from the data address counter 12, and an address matching signal of the address matching circuit 32. and a trigger signal from the trigger circuit 14, a display section 33 that stores and displays each data out signal from the data bank 13, and an address match signal from the address match circuit 32 and a contact point of the control switch. Each of the control units 6 includes a control unit 6 that sends an AND signal with the selection code configuration circuit 15 to the selection code configuration circuit 15, and displays a selection completion indication under the condition that the selection completion signal from the selection completion detection circuit 16 and the contact of the control switch are turned on. The panel section 2 includes a plurality of control display units 7 and a bus line section BL for common wiring of input/output signals of each control display unit 7, and each control of the logic control section 1 and the panel section 2 is provided. The data address signal line, the data out signal line, the trigger signal line, the selection completion signal line, and the signal line from each control section 6 to the selection code configuration circuit 15 connecting the display units 7 are connected to the bus line. A simultaneous scanning data display/switch status collection circuit characterized by common wiring via part BL.