HU200513B - Circuit arrangement for controlling claviature and display - Google Patents

Abstract

FIELD OF THE INVENTION The present invention relates to a circuit arrangement for controlling a keyboard and a display comprising a control unit (3) having a first bus output (31), a display state controller having a line (j), via a first bus (B1) to the bus input of the display control unit (1). , second input (35) output (61) of timing unit (6), bus output (12) of display control unit (1), display matrix controller with line "k" via bus 2 (B2) to bus input (2) bus bus (2) 21). The circuit arrangement further comprises a column selection coding unit (4) having a bus input (41) via a third bus (B3) which controls a column selection containing a line "l" to a second bus output (32) and a comparing unit (3) of the control unit (3). 7) at the first bus input (71), the bus output (42) is connected to a bus input (51) of a matrix (5) switching through a "m" line through a fourth bus (B4). Bus output (52) of the switch matrix (5) via bus 6 (B6) of the line sensor unit (8) through the sixth bus (B6) indicating line line "p", bus line output (81) of line sensor unit (8) The second bus input (73) of the comparing unit (7) and the bus input (33) of the control unit (3) are connected via a fifth bus (B5) identifying the line state containing the line. The output (72) of the reference unit (7) is connected to the first input (34) of the control unit (3), the third bus input (74) to the first bus output (31) of the control unit (3). Figure 1 Scope of the description: 8 pages, Figure 2 -1-

Description

BACKGROUND OF THE INVENTION The present invention is a circuit board arrangement for controlling a keyboard and a display.

The circuit arrangement of the present invention is preferably used in equipment having a keypad (control) as a foil keypad unit.

There are several options for controlling the keyboard and display. equipment is known. It represents the technical level e.g. LOCATOR 7201 from SOLATRON - SCHLUMBERGER for universal debugging. The solution used in this machine is that not all keyboards are selected on the foil keypad, only the most important ones. The unit has a microprocessor-based control unit that determines which controls are being pressed and what displays are to be made.

The disadvantage of this solution is that it may be possible to press a control that is not currently valid and does not make sense, in which case an error message will be issued and de-icing is not possible. A further disadvantage is that the keyboard is controlled by the control unit and therefore the display is slower.

It is an object of the present invention to overcome the shortcomings of the known solution and to provide a circuit arrangement in which

- in each condition of the device to be treated, all controls that are currently valid are marked;

- only selected and designated controls can be operated;

- without the control unit, it is possible to decide whether the selected controls are the (permitted) controls selected in a given state;

- the foil keypad provides an anti-glare keyboard.

The circuit arrangement of the present invention is based on the recognition that when a control unit is selected from a column selection coding unit, associated switching matrix, a switching matrix detection unit and a comparator unit associated therewith, the display state control signals, the column select control signals and the determines whether a given switch matrix element is in the set of switch matrix elements allowed in the display matrix from a combination of identifiers, and if so, indicates to the control unit via the signal output of the subset the operation of the enabled switch matrix element; designated controls operate.

The present invention thus relates to a circuit arrangement for controlling a keyboard and a display comprising a control unit having a first bus output, a display status controller comprising a j "line via a first bus to a display control unit bus input, a second input to a timing unit output, a" k " is connected to the bus input of the display matrix. The circuit arrangement further comprises a column selection coding unit having a bus input via a third bus containing a "1" line selection column to a second bus output of a control unit and a first output of a comparator unit via a fourth column 2 bus containing a "m" line. is connected to the bus input of the matrix. The switch matrix bus output is connected to a queue detector bus input via a sixth bus with a line status indicator having a "p" line, a fifth bus input to the comparator unit via a fifth bus to the queue detector bus with a queue identifier containing line "η" 'and the control unit bus input. The output of the comparison unit is connected to the first input of the control unit, and the third bus input is connected to the first bus output of the control unit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail with reference to the following drawings, which are:

Figure 1 is a block diagram of a circuit arrangement according to the invention;

Figure 2 illustrates a preferred embodiment of the comparison unit.

1 illustrates a circuit arrangement according to the present invention comprising a control unit 3 having a first bus output 31, a display status controller having a j "line through a first bus B1 to a bus input 11 of a display control unit 1 and a second input 35 to the output 61 of a timer unit. , the bus output 12 of the display control unit 1 is connected to the bus input 21 of the display matrix 2 via a second bus B2 of a display matrix controller having a k 'line. The circuit arrangement further comprises 4 column selection coding units having a bus input 41 via a third bus B3 controlling a "álaszt line" column selection to the second bus 32 of the control unit 3 and the first bus input 71 of a comparator 7 having a "m" bus output. A line selector is connected to the bus input 51 of the switch matrix via a fourth bus B4. The bus output 52 of the switching matrix 5 has a line status indicator having a "p" line through bus 6 B6 to bus input 82 of a row detector unit 8, and a fifth line B5 having a line status identifier via bus B5 via bus 5 of bus 8. It is connected to the bus input 73 and the bus input 33 of the control unit 3. The output 72 of the comparison unit 7 is connected to the first input 34 of the control unit 3, and the third bus input 74 is connected to the first bus output 31 of the control unit 3.

Figure 2 illustrates a preferred embodiment of the comparator unit 7, characterized in that the comparator unit 7 comprises a matrix element encoding unit 7A whose bus inputs form the first bus input 71 and the second bus input 73 of the comparator unit 7. The bus output of the matrix element encoder 7A is connected to one of the bus inputs of the comparator 7B and the other bus inputs of the comparator 7B to the bus output of the display status encoder 7C. The output of the comparator 7B is the 72 is the bus input.

The circuit arrangement according to the invention operates as follows:

Each display unit of the display matrix 2 is mechanically assigned to a corresponding switch element of the switch matrix 5. This mechanical and logical assignment ensures that a

EN 200513 Β in each condition of the equipment to be operated in its respective state - "intelligently operated" switching elements may be displayed and the operation of the current switching unit may be indicated when each switching element is actuated.

The current status of the equipment to be treated is determined by the control unit 3. The current status display information is defined as a set of switch matrix points 5 that can be validated in a given state via the first bus output 31 of the control unit, which is transmitted through the first bus B1 to the display state controller 1B. 11, and the third bus 74 of the comparator unit 7. The display control unit 1, by decoding the information received at its bus input 11, controls the corresponding display units of the display matrix 2 via its bus output 12 and via the second bus B2 of the display matrix controller containing the line Jc '. The scheduling of the control unit 3 is controlled by its second input 35 via a sampling signal at the output 61 of the timing unit 6. The control unit 3 controls the column select coding unit 4 and the comparator unit 7 via the second bus output 32 of the control unit and the third bus B3 controlling the column selection containing the line "1". The column selection coding unit drives the corresponding column of the switching matrix 5 via the fourth column B4 bus containing the "m" line after decoding the information received at the bus input 41. The signal level change generated by actuation of any of the switching elements of the switching matrix 5 is transmitted to the bus input 82 of the line detector unit 8 via a sixth bus B6 indicating the line status "ρ" '. After proper level conversion, the row detector unit 8, via its bus output 81, transmits to the fifth bus B5 the line status identifier containing the line number 'ri', which is transmitted to the bus input 33 of the control unit 3 and the second bus input 73 of the comparator unit. Comparison unit 7 provides information on the first bus information B1 for the display status controller for the third bus input 74, third bus information for the third bus B3 on the first bus input 71, and third bus information 73 for the second bus input 73. combining information from a fifth B5 bus information of a queue identifier having a line number '', determines whether a particular element of the switch matrix 5 is in the set of enabled switch matrix elements in the display matrix 2. If the current switch matrix element is in the set of enabled switch matrix elements, then a subset that appears through the output of the comparator unit 7 indicates to the control unit 3 the operation of the enabled switch matrix element,

The control unit 3 evaluates the queue state information received at the bus input 33 and performs the necessary interventions to control the equipment to be managed, and determines the next current state by the subset signaling signal received at its first input 34.

In a preferred embodiment of the circuit arrangement according to the invention, the display control unit 1 is used

Consisting of TTL level logic gate circuits, decoders, level adapters, the display matrix 2 is preferably constructed from LED light elements. The control unit 3 is a microcomputer system with an interrupted architecture, the column selection coding unit 4 comprises logic gate circuits, level matching circuits, and oscillator circuits in the case of capacitive design of the switching matrix. The switch matrix 5 is made up of switch elements, a foil keypad design, the timer unit 6 includes timer counting circuits with an internal clock. The comparator unit 7 consists of PROMs and TTL level logic gate circuits and the row detector unit 8 comprises TTL level logic gate circuits.

The objects and advantages of the circuit arrangement according to the invention are as follows:

- allows visually clear, easy-to-use, "guided" controls by marking each control with the currently valid controls;

- only selected and designated controls can be operated;

- the comparison unit relieves the control unit of other functions from the continuous inspection of the display control unit, since it is only concerned with checking the matrix elements that join the specified subset;

- a convenient design of the comparator unit ensures that the elements of the switching matrix are flicker-free;

- architecture allows for flexible, flexible control equipment (tabular control information stored in PROM).

Claims (2)

PATENT CLAIMS A circuit arrangement for controlling a keyboard and a display comprising a control unit (3) having a first bus output (31), a display status controller comprising a j "line via a first bus (B1) to a bus input (11) of a display control unit (1). the input (35) to the output (61) of the timing unit (6), the bus output (12) of the display control unit (1) to the bus input (21) of the display matrix controller via a second bus (B2) with a "k" line. further comprising a column selection coding unit (4) having a bus input (41) via a third bus (B3) controlling a column selection containing a "Γ" line, to a second bus output (32) of the control unit (3) and a comparator. a matrix for switching the first bus input (71) of the unit (7) to the bus output (42) via a fourth column selector bus (B4) having a "m" line (5) to the bus input (51), the bus output (52) of the switch matrix (5) via the bus state (6) of the queue detector unit (8) via the sixth bus (B6), the queue detector unit (8) bus output (81) to a second bus input (73) of the comparator unit (7) and a bus input (33) of the control unit (3), via the fifth bus (B5) identifying the queue status line containing the line 'ri'; 72) the first be3 of the control unit (3) EN 200513 Β thread (34), the third bus input (74) is connected to the first bus output (31) of the control unit (3). Circuit arrangement according to claim 1, characterized in that the comparator unit (7) comprises a matrix element encoding unit (7A), the bus inputs of which are the first bus inputs (71) and the second bus inputs (73) of the comparator unit (7). ), the bus output is connected to one bus input of the comparator (7B), the other bus input of the comparator (7B) is connected to the bus output of the display status encoder (7C), the output of the comparator (7B) is the output (72) of the comparator unit The bus input (7C) is the third bus input (74) of the comparator unit (7).