JPS5930305B2 - Lock management method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lock management method for locking specific information on main memory in an information processing apparatus to protect it from being accessed by others.

Conventionally, methods using test and set instructions (TS) and conveyor and swap instructions (CS) are known as methods for locking information on main memory. T.S.
The instruction checks whether the byte indicated in the address field of the instruction is ``1'', and if it is not ``1'', it is set to ``1'', and the central processing unit checks whether it is ``1'' or not. This is a command to notify the (CPU) side.

When using this TS instruction, a byte at a specific address is prepared as a lock byte corresponding to the information to be locked, and when a certain process accesses information that requires locking, this corresponding locking byte is prepared. Execute a TS instruction on a byte. As a result of executing this instruction, if it is detected that the lock byte was previously "o", the target information is processed.

In addition, if the lock byte is already ``1'' and it is locked by another, processing is carried out.This procedure can prevent logical contradictions such as accessing specific information at the same time. However, in this method, even if information originally requires a head check, programs that do not go through the regular procedure, that is, programs that are programmed to access information directly without executing the TS command, cannot be accessed from this program. The drawback is that the information that should be locked is simply accessed, and the lock is not checked.

On the other hand, the CS instruction also has the same drawback as the TS instruction in that locking is disabled for programs that do not go through the regular procedure using the CS instruction ◆.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a lock management system that completely protects information in main memory in order to overcome these drawbacks. In the present invention, a special management table is provided to hold addresses of information to be locked, and machine language instructions are provided for registering and canceling information addresses in this management table.

In other words, this table is searched for every access to main memory, and if there is an access from a process other than the one that performed the lock, the program notifies the CPU as an exception event, instead of going through the normal procedure. Information can also be locked against access, and specific information is completely protected. By the way, there is also known a method of managing locks by preparing a management table having entries corresponding to storage positions of information to be locked in the main memory and setting lock bits in this table.

However, in such a system, it is necessary to prepare an entry in the management table for all information that may be accessed, for example, for every block in main memory. The disadvantage is that the capacity is large.

However, in computer systems, it is known that the number of pieces of information that must be simultaneously locked at a certain point in time is extremely small compared to the total number of pieces of information existing in the main memory.

In the present invention, a management table is provided that has entries equal to the number of pieces of information to be simultaneously locked, and the address of the information to be locked is registered in this table when lock management becomes necessary. According to the present invention, a lock management system can be implemented using relatively small-capacity hardware.

Furthermore, in the present invention, as a special command for lock control, a test and check is performed to check whether the information is registered in the management table, and if it is not locked, to register it in this. Lock life +T
A reset lock command RL is provided to release the lock registered in the lock control table L and the management table.
Next, the present invention will be explained in detail with reference to the drawings. Embodiments of the present invention will be described below. In the following description, information is locked in units of words in the main memory. First, a first embodiment of the present invention will be described with reference to FIG.

In this embodiment, the management table that holds the addresses of information to be locked is constituted by an associative memory AM.

The number of words in the content addressable memory AM is determined by the expected number of information to be simultaneously locked in the computer system and the cost of the content addressable memory AM. Also, associative memory A
Each word of M (hereinafter referred to as entry 1) contains a process number field PI that holds the process that has the lock.
DL A lock address field LA holding the address of information to be locked and a valid bit field V indicating whether these fields are valid or not.
Consisting of The associative memory AM searches its contents using the search data and the mask data, and the mask data is “1”.
If the value of the search data corresponding to the bit position `` and the information on the associative memory all match, 01'' is output to the corresponding word line WL, otherwise ``0'' is output. This is a well-known associative memory.

Here, a mask register MR is prepared, one word on this register is selected, and its contents are input to the content addressable memory AM as mask data MD.

Further, as search data, word address WA and valid bit information VD from CPU1 to process number PN1 main memory are applied. Furthermore, the word line WL that outputs the matching information from the content addressable memory AM is input to a priority circuit encoder (hereinafter simply referred to as an encoder) ECD. This selects the highest line with a value of ``11'' among the input word lines, outputs this position, that is, the word address WS with the matching content as a binary value, and at the same time selects one of the input word lines. This circuit outputs a coincidence detection signal F when a value of 61'' is present in any of the inputs, and a mismatch signal NF when there is no value of ``1'' in any of the inputs. Next, the operation of this embodiment will be explained in detail.

When the TL command is executed by the CPU 1, a lock command SL is applied to the control circuit 4 of the lock mechanism 3, and at the same time, the number PN of the process that instructed execution and the address WA of the information to be locked are applied to the content addressable memory AM. .

In response to the lock command SL, the control circuit 4 performs the following control operation to search whether this information has already been registered in the content addressable memory AM for locking. First, from among the mask patterns in the mask register MR, a mask pattern in which the lock address field LA and valid bit V of the associative memory AM have a value of "1" is selected and applied to the associative memory AM.

As a result, when the encoder ECD outputs the coincidence signal F,
That is, if the information specified by the address WA of the information to be locked has already been locked, a failure signal F is sent to the CPU1. On the other hand, when the encoder ECD outputs the mismatch signal NF, that is, when the designated information is currently not locked, the following processing operation is performed.

That is, of the mask patterns in the mask register MR, a mask pattern with only valid bit fields of 61'' is selected and applied to the associative memory AM, and "0" is applied as search data VD of the valid bit fields.

When the encoder ECD outputs the mismatch signal NF, i.e.
If there is no space in the management table, a failure signal F is sent to CPU1. When the encoder ECD outputs the signal F, the values of the process number PN and the main memory word address WA from the CPU1 and the valid bits are added to the associative memory address output from the encoder ECD.
1'' is written and a success signal S is sent to the tag CPUl.C
When the lock release command is executed by PUl, the release finger +RL is sent to the control circuit 4 of the log mechanism 3, and the associative memory AM receives the release finger +RL.
The process number PN that executed this instruction and the address WA of the information to be released are applied.

The Fbl leg circuit 4 performs the following control operation using this finger +RL. That is, from the mask register MR to the content addressable memory AM
Select a pattern with all fields of 61″, and combine this with C
Associative memory AM with process number PNl applied from PUl and main memory word address WA and valid bit "1".
, and set the effective bit field of the word in the associative memory AM where a match is detected to 60''.If the word in the associative memory A
If no match is found in M, an error occurs in C.
PUl will be informed. Furthermore, the lock mechanism 3 performs the following operations for all accesses to the main memory.

That is, when the associative memory AM is searched using the mask pattern 617 for the valid bit field v and the lock address field LA as mask data, and the main memory word address WA and valid bit 61'' as search data, and a match is detected. Then, by masking all the fields of the associative memory AM to 61'', the associative memory A
When M is searched and a mismatch is detected, this indicates that a process other than the one that performed the lock has illegally accessed the locked information, and this is notified to the CPU1 as an exception event.

In other cases, the access is considered normal and no action is taken. Next, a second embodiment of the present invention will be described with reference to FIG.

In this embodiment, the management table is realized by a method called a set associative method using a normal access random memory instead of an associative memory. Figure 2a
As shown in FIG. 2, the word address of the main memory 2 is divided into a lower set address section SA and an upper word address section WA, and the set address RA is used as the random access memory address of the management table. That is, each word of the management table T specified by the set address SA can hold two pieces of lock information. Furthermore, an entry is provided corresponding to each piece of lock information. Each entry has process number fields PNl, PN2 and word address fields WAl, WA as in the first embodiment.
2 and valid bit fields Vl, V2. The values of the process number fields PNl, PN2 and the word address fields WAl, WA2 of the management table T are applied to the comparison circuits Cll, Cl2, C2l, C22, and the word address in the main memory 2 address of the process number PNl from the CPUl WA is applied to the corresponding field of the management table T and the corresponding comparison circuit. Next, the operation of this embodiment will be explained in detail.

In this embodiment, the search is performed by reading the word of the management table T specified by the set address section SA of the main memory address, and comparing the values of the process number fields PNl, PN2 and word address fields WAl, WA2 with the comparison circuits Cl2, C22. , Cll, C2l
This is done by comparing the process number PN from l to the word address field WA.

If the searched address is registered in one of the two entries in the management table T, the corresponding comparison circuit outputs a match signal, thereby confirming that it is registered in the management table T. can be detected. Registration in the management table T is performed by writing the process number PN and word address WA to be registered in entry 1 specified by the selection bit of the word of the management table T specified by the set address SA.

The operation of the lock mechanism 3 in response to instructions from the CPU 1 and the operation when accessing the main memory 2 are functionally the same as in the first embodiment, except for the search method.
A detailed explanation will be omitted here. As described above using the embodiments, the present invention is characterized by providing a special management table for managing locks, registering information to be locked in this table, and registering information to be locked in this table. The purpose is to detect unauthorized access to locked information by searching the management table.

Therefore, various modifications can be made to the present invention; for example, the first and second embodiments are configured to detect all accesses by processes other than registered processes; It is also possible to configure the device to lock on a specific type of access, such as detecting only writes. In this case, the above-mentioned lock is performed by providing an access field in the management table and registering the type of access to be prohibited in this field. Further, in this embodiment, information is locked in units of words, but it is also possible to lock information in units of blocks of a fixed length or in units of pages.

Further, by providing several management tables, it may be configured such that locking can be performed in units of words, blocks, or pages. Furthermore, a management table with an equivalent function can be realized using a single associative memory with a self-masking function. Furthermore, although it was assumed that a real address would be used as the main memory address, it is also possible to use a virtual address in a virtual memory computer system instead.
Further, in the above embodiment, the process number that issued the lock command is registered in the management table, but the process number specified by the command may be registered. Furthermore, although the management table is said to be searched using the process number and word address of the process that executed this instruction when releasing the lock, it is also possible to configure the management table to be searched using only the word address.

Alternatively, the process number may be specified in the lock release command. Further, in the first embodiment, the detailed configuration of the control circuit 4 is not directly related to the gist of the present invention and can be easily realized using conventionally known circuits, so the detailed configuration is omitted here.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention.

Claims (1)

[Claims] 1 A method for managing locking operations for accesses made by processes executed on a central processing unit to specific information in main storage, in which a number of entries equal to the number of pieces of information to be simultaneously locked at a certain point in time is A process number field that holds the number of the process that requested locking for each entry using a management table whose contents are registered and canceled according to instructions from the central processing unit, and an address field that holds the address of the information to be locked. and a valid bit field indicating the validity of the contents of the entry itself, so that this management table is referenced during all accesses to the main storage, and processes other than the process that performed the lock are registered in the management table. 1. A lock management system characterized in that when accessing information that is currently being accessed, this is detected and notified to the central processing unit as an exceptional event.