JPS5928710A - Variable gain control circuit - Google Patents
Variable gain control circuitInfo
- Publication number
- JPS5928710A JPS5928710A JP13877082A JP13877082A JPS5928710A JP S5928710 A JPS5928710 A JP S5928710A JP 13877082 A JP13877082 A JP 13877082A JP 13877082 A JP13877082 A JP 13877082A JP S5928710 A JPS5928710 A JP S5928710A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- variable gain
- gain control
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3084—Automatic control in amplifiers having semiconductor devices in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明はディジタル元信号を受信する光受信系において
安定な可変利得制御のできる回路に関１−る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a circuit capable of stable variable gain control in an optical receiving system for receiving digital original signals.
ディジタル元信号娶受信する光受信系は帰還による利得
制御を２段にかけている。即ち第１図に示す回路構成図
において、光信号入力が入力端子ＩＮに印加され、アバ
ランシェフォトダイオードＡＰＤ→前置増幅器ＰＲＡ→
可変利得制御増幅器ＡＧＣｉＡ→後段増幅器ＰＳＡ乞経
て図示しない識別器に到達し、ディジタル信号の有無’
ｋ ｍ ＦＪＪする。後段増幅器ＰＳＡの出力の一部は
帰還回路により可変利得制御を行なうため、ピーク検出
回路ＰＤ、比較増幅器ＯＰＡ、ダイオードスイッチＤ８
１ 、ＤＳ２を介して可変利得制御増幅器ＡＧＣＡへの
制御電圧Ｖ２゜アバランシェフォトダイオードＡＰＤ制
御用ＤＣ−ＤＣコンバータへの制御電圧Ｖ３奢４る。The optical receiving system that receives the original digital signal has two stages of gain control using feedback. That is, in the circuit configuration diagram shown in FIG. 1, an optical signal input is applied to the input terminal IN, and avalanche photodiode APD → preamplifier PRA →
Variable gain control amplifier AGCiA→post-stage amplifier PSA and then reaches a discriminator (not shown), which detects the presence or absence of a digital signal.
km FJJ. Since a part of the output of the rear stage amplifier PSA performs variable gain control using a feedback circuit, a peak detection circuit PD, a comparator amplifier OPA, and a diode switch D8 are used.
1, a control voltage V2 is applied to the variable gain control amplifier AGCA via DS2, and a control voltage V3 is applied to the DC-DC converter for controlling the avalanche photodiode APD.
ＤＣ−Ｉｌｌコンバータの出力はアバランシェフォトダ
イオードＡＰＤ’４制御する。比較増幅器ＯＰＡはピー
ク検出回路ＰＤの出力と基準電圧Ｖｓとの差を増幅し、
帰還基準電圧ｖ１としている。The output of the DC-Ill converter is controlled by an avalanche photodiode APD'4. The comparison amplifier OPA amplifies the difference between the output of the peak detection circuit PD and the reference voltage Vs,
The feedback reference voltage is set to v1.
この電圧は入力端子ＩＮの電圧と密接な関係にあるため
１．入力信号と考えて良い。今元人カレベルが所定値以
下の時は電圧ｖ２が一定値で電圧ｖ３は制御動作状態と
なり、元入力レベルが所定値以上のときは電圧■３が一
定値で、■２が制御動作状態になる。そのためダイオー
ドスイッチＤＳ１ 、ＤＳ２により切換えを行ない、変
動する入力レベルに対１−出力を安定化する帰還増幅回
路を得ている。This voltage is closely related to the voltage at the input terminal IN, so 1. You can think of it as an input signal. When the current input power level is below a predetermined value, voltage v2 is a constant value and voltage v3 is in a control operation state, and when the original input level is above a predetermined value, voltage ■3 is a constant value and ■2 is in a control operation state. Become. Therefore, switching is performed using diode switches DS1 and DS2 to obtain a feedback amplifier circuit that stabilizes the output with respect to the fluctuating input level.
（３） 従来技術と問題点
第１図に示すダイオードスイッチにおいて参照電圧Ｖｒ
ｉ、Ｖｒ２と使用するダイオードの特性の違いなどのた
め、前記Ｖ２ 、 Ｖ５の動作切換の所定値は、常に同
一になるとは限らず、第２図人に示すように重なり合っ
たり、また第２図Ｂに示すように隙間を生じる。重なり
合うときは入力レベルの変動に対し一定化する制御動作
のループ回路が併存するため不安定となり発振動作を起
すことがある。また隙間馨生じるときは識別器入力信号
の振幅変ｋｂ量が隙間のレベルだけ増大する。また隙間
となっている入力電圧値に対しては変動が起っても検出
することができない。動作切換の所定値ケ揃えるために
は参照電圧Ｖｒ１ 、 Ｖｒ２の値を個々の回路毎に調
整する必要があった。(3) Prior art and problems In the diode switch shown in Figure 1, the reference voltage Vr
Due to differences in the characteristics of i, Vr2 and the diodes used, the predetermined values for switching the operation of V2 and V5 are not always the same, and may overlap as shown in Figure 2, or may overlap as shown in Figure 2. A gap is created as shown in B. When they overlap, a loop circuit for control operation that stabilizes input level fluctuations coexists, which may result in instability and oscillation. Further, when a gap occurs, the amplitude change kb amount of the discriminator input signal increases by the level of the gap. Further, even if a fluctuation occurs in the input voltage value that is a gap, it cannot be detected. In order to match the predetermined values for operation switching, it was necessary to adjust the values of the reference voltages Vr1 and Vr2 for each circuit.
（４）発明の目的
本発明の目的は前述の欠点を改善し、無調艶で切換点を
一致ｊる回路により安定な可変利得ｆｆ１ｌＪ ＃；ｌ
ｌのできる回路馨提供することにある。(4) Object of the Invention The object of the present invention is to improve the above-mentioned drawbacks, and to provide a stable variable gain ff1lJ #;l by a circuit that is atonal and has matching switching points.
The purpose is to provide a circuit that can be used.
（５）発明の構成
本発明の構成は、光受信入力の印加されるアバランシェ
フォトダイオードと該フォトダイオード出力の印加され
る可変利得制御増幅器とを有し、該増幅器出力？信号識
別装置に入力すると共に前記アバランシェフォトダイオ
ードと可変利得制御増幅器に帰還し、増倍率と利得を個
別に制御する元信号の可変利得制御回路において、前記
各構成膜利得を個別に制ｕ−ｒるための信号通過切換装
置を有し、該切換装置はスレショルド電圧と利得制御電
圧トの入力端子と、アバランシェフォトダイオードと可
変利得制御増幅器への出力端子とを有する２個の差動対
で構成されている。(5) Configuration of the Invention The configuration of the present invention includes an avalanche photodiode to which an optical reception input is applied, and a variable gain control amplifier to which the photodiode output is applied, and the amplifier output? In a variable gain control circuit for an original signal that is input to a signal identification device and fed back to the avalanche photodiode and variable gain control amplifier to individually control the multiplication factor and gain, the gain of each component film is individually controlled. The switching device comprises two differential pairs having input terminals for a threshold voltage and a gain control voltage, and output terminals for an avalanche photodiode and a variable gain control amplifier. has been done.
（６）発明の実施例
以下図面に示す本発明の実施例について説明する。第６
図は本発明の構成を第１図と対応させて示すもので、第
１図におけるダイオードスイッチＤＳ１ 、ＤＳ２
の部分ンスイッチ回路ＳＷに変更し、その結果第４図に
示す大田力特性図が得られ、第５図乃至第７図にスイッ
チ回路の具体的構成例を示している。第４図において、
ｖｔｈはスレショルドレベルの所定値を示し、この電圧
を境として、帰還制御動作の回路が確実に切換えされる
。したがって帰還制御の動作が安定化する。(6) Embodiments of the invention Examples of the invention shown in the drawings will be described below. 6th
The figure shows the configuration of the present invention in correspondence with FIG. 1, and shows the diode switches DS1 and DS2 in FIG.
As a result, the Ota force characteristic diagram shown in FIG. 4 is obtained, and specific configuration examples of the switch circuit are shown in FIGS. 5 to 7. In Figure 4,
vth indicates a predetermined value of a threshold level, and the circuit for feedback control operation is reliably switched at this voltage. Therefore, the operation of feedback control is stabilized.
第５図に示す面１路図は本発明におけるスイッチ回路の
具体的構成を示し、差動対ＤＦＴ１と差動対ＤＦＴ２と
を設け■１．ｖ２．ｖ３．ｖｔｈは第４図に示す電圧値
を示し、ＶＸＸは動作電源ν）一方の端子、ＧＮＤは同
′ｄＬ源の他方の端子、Ｑ１〜Ｑ８はトランジスタを示
す。各差−殆ＦＴ１゜ＤＦＴ２は各２個のトランジスタ
Ｑ５． Ｑ６１Ｑ７１Ｑａヲｆｉ用し、各トランジスタ
のエミッタは抵抗を介して共通接続し、差動対の各一方
のトランジスタＱ６ 、 Ｑ７０ベース同志を接続しそ
の電圧をｖｂとする。また差動対のＤＦＴｌの他方のト
ランジスタＱ５のベース電圧をｖａ ＋ 差動対Ｄ Ｆ
Ｔ ２の他のトランジスタＱ８リペースｍｌ■ｏとす
る。トランジスタＱ３．Ｑ４０ベース・エミッタ間の電
圧を■□とすると
ｖ、 ＝ Ｖｊ −ｖＢ。The side-by-side diagram shown in FIG. 5 shows a specific configuration of the switch circuit according to the present invention, in which a differential pair DFT1 and a differential pair DFT2 are provided. v2. v3. Vth indicates the voltage value shown in FIG. 4, VXX indicates one terminal of the operating power supply ν), GND indicates the other terminal of the same dL source, and Q1 to Q8 indicate transistors. Each difference - almost FT1°DFT2 is each two transistors Q5. The emitters of each transistor are commonly connected through a resistor, and the bases of transistors Q6 and Q70 of each one of the differential pair are connected together, and the voltage thereof is set to vb. Also, the base voltage of the other transistor Q5 of the differential pair DFTl is va + differential pair D F
Let the other transistor Q8 of T2 be replaced by ml o. Transistor Q3. If the voltage between the base and emitter of Q40 is □, then v, = Vj - vB.
Ｑｔｈ−ＶＢＫ
Ｖｂ ＝ Ｖ、ｈ−ＶＢＥ （Ｖ、＜ Ｖ、ｈのとき）
Ｖｂ＝ Ｖｌ ｖａｘ （Ｖｌ＞ Ｖｔｈのとき）の
関係にある。差動対ＤＦＴ１がらの出力電圧を■３．同
ＤＦＴ２からの出力電圧をＩ２として帰還制御に使用す
る。今ｖ、 ＞ ＶｔｈのときトランジスタＱ、がオン
、Ｑ２がオフとなってｖｌは、■、−ｖＢＫとなるが、
ｖｂはＩ１と同電位で、Ｉ６は一定のままである。一方
■。はｖｔｈ −ＶＢＥで一定であり、ｖｂが■、に応
じる変化をしているから、Ｉ２はｖ、−ｖｔｈの差で変
化する。Qth-VBK Vb = V, h-VBE (when V, < V, h)
The relationship is Vb=Vlvax (when Vl>Vth). 3. The output voltage from the differential pair DFT1. The output voltage from the DFT2 is used as I2 for feedback control. Now, when v, > Vth, transistor Q is on and Q2 is off, and vl becomes -vBK, but,
vb is at the same potential as I1, and I6 remains constant. On the other hand ■. is constant at vth -VBE, and since vb changes according to (2), I2 changes depending on the difference between v and -vth.
Ｉ４ ＜ Ｖｔｂのときは逆Ｋ Ｉ２が一定で、Ｖ３カ
■１とＶｔ、ｈの差に応じて変化する。When I4 < Vtb, the inverse K I2 is constant and changes depending on the difference between V3 force 1 and Vt, h.
次に第６図はスイッチ回ｉ＠ ｓ ｗとして第５図を僅
かに変形させたものである。今ｖ１〉Ｖｔｈのときｖ１
ｖＢｇ＝ｖｌ冨ｖ。、 Ｖｂ−Ｖｔｈ−ＶＢｇで一定で
あるから、Ｉ２はｖｌに従って変化する。すなわちＶ、
＝ Ｖｏのため差動対に流れ込む電流についてＩｔ
＝ Ｉ４ 、 Ｉ、 −１３となり。Next, FIG. 6 is a slightly modified version of FIG. 5 as a switch circuit i@sw. Now v1〉Vth then v1
vBg=vlfuv. , Vb-Vth-VBg are constant, so I2 changes according to vl. That is, V,
= It for the current flowing into the differential pair due to Vo
= I4, I, -13.
Ｉ、、Ｉ、の合計がＲ１に流れる。Ｉ２ ＝ Ｉ３のた
めＩ、 ＋Ｉ３＝ １１＋Ｉ２そして１１＋ Ｉ２＝
Ｉ。という定電流のの＊流イ直となるので出力ｖ３が一
定である。ｖｌりｖｔｈのときはＶＣ＝ ｖｔｉｌ−Ｖ
ＢＫ＝■、であってＩ２が一定となる。すなわち工３が
一定でＩ１はＩ１の変化に従うためＩ１はＩ１に従って
変化する。工５が一定であるため１１とＩ３の和の電流
即ちＩ３の値はｖｌに従って変化する。The sum of I,,I,flows to R1. I2 = I3 so I, +I3= 11+I2 and 11+ I2=
I. Since the constant current is constant, the output v3 is constant. When vl is vth, VC= vtil-V
BK=■, and I2 is constant. That is, I1 changes in accordance with I1 because I1 follows the change in I1 while I1 is constant. Since the current 5 is constant, the current sum of 11 and I3, that is, the value of I3 changes according to vl.
第７図は第４図におけるＱ１〜Ｑ４のトランジスタをＤ
１〜Ｄ４のダイオードに置換した場合を示し、動作は同
じである。Figure 7 shows the transistors Q1 to Q4 in Figure 4.
The case where diodes 1 to D4 are replaced is shown, and the operation is the same.
（７）発明の効果
このよう圧して本発明によるとフォトダイオードと自動
利得制御回路との帰還ループが。(7) Effects of the Invention According to the present invention, a feedback loop between a photodiode and an automatic gain control circuit is provided.
所定の切替電圧において無調整で切替えられ、その切替
点が無調整で所定値となるから、回路の動作が安定とな
る。Since switching is performed without adjustment at a predetermined switching voltage, and the switching point becomes a predetermined value without adjustment, the operation of the circuit becomes stable.
第１図は従来の可変利得制御回路の構成を示す図、第２
図は第１図の動作特性図、第３図は本発明の原理構成図
を示し、第４図は第６図の動作特性図である。第５図乃
至第７図は第３図中のスイッチ回路の具体的構成を示す
図である。
ＡＰＤ ・・・アバランシェフォトダイオ−、ドＡＧ
ＯＡ・・・可変利得制御増幅器
ＤＳ１ 、ＤＳ２・・・ダイオードスイッチｖｔｈ・・
−スレショルドレベル
ＤＦＴＩ、ＤＦＴ２・・・差動対
特許出願人 富士通株式会社（ほか１名）代理人弁理土
鈴木栄祐
第１図
ＶＩ Ｖ１
第２図Ａ 第２図８■１
第４図
第５図
第６図
第７図Figure 1 shows the configuration of a conventional variable gain control circuit, Figure 2 shows the configuration of a conventional variable gain control circuit.
The figure shows the operating characteristic diagram of FIG. 1, FIG. 3 shows the principle configuration diagram of the present invention, and FIG. 4 shows the operating characteristic diagram of FIG. 6. 5 to 7 are diagrams showing specific configurations of the switch circuit in FIG. 3. APD ・・・Avalanche photodiode, AG
OA...Variable gain control amplifier DS1, DS2...Diode switch vth...
-Threshold level DFTI, DFT2... Differential pair patent applicant Fujitsu Limited (and one other person) Patent attorney Eisuke Tsuchi Suzuki Figure 1 VI V1 Figure 2 A Figure 2 8■1 Figure 4 Figure 5 Figure 6 Figure 7
Claims (1)
オードと該フォトダイオード出力の印加される可変利得
制御増幅器とを有し、該増幅器出力を信号識別装置に入
力すると共に前記アバランシェフォトダイオードと可変
利得制御増幅器に帰還し、増倍率と利得を個別に制御す
る元信号の可変利得制御回路において、２つの差動対を
構成するトランジスタの内の一方のトランジスタのペー
スを共通に接続し、該増幅器出力と基準電圧との大小関
係により、いずれか一方の差動対のペース電位を異なら
３゜せることにより、該２つの差動対より鞠られるア
バランシェフォトダイオードと可変利得制御増幅器への
制御信号の一方を変化させることを特徴とする可変利得
＃ＪＯ御回路。 トダイオードと該フォトダイオード出力の印加される可
変利得制御増幅器とを有し、該増幅器出力を信号識別装
置に入力すると共に前記アバランシェフォトダイオード
と可変利得制御増幅器に帰還し、増倍率と利得を個別に
制御する光信号の可変利得制御回路において、２つの差
動対Ｙｍ成するトランジスタの内の一７ｊのトランジス
タのペースを共通に接続し、該増幅器出力と基準電圧と
の大小関係により、いずれか一方の差動対ＶＣ流れる電
流を異ならせることＫより、該２つり差動対より得られ
ルアバランシェフオドダイオードと可変＋ｕｉ制御増幅
器への制御信号の一刀を変化させることを特徴とする可
変利得制御回路。[Claims] 1. An avalanche photodiode to which an optical reception input is applied, and a variable gain control amplifier to which an output from the photodiode is applied, the output of the amplifier being input to a signal identification device, and the avalanche photodiode to which an optical reception input is applied. In the variable gain control circuit for the original signal that feeds back to the diode and the variable gain control amplifier and controls the multiplication factor and gain individually, the paces of one of the transistors that make up the two differential pairs are connected in common. By changing the pace potential of one of the differential pairs by 3 degrees depending on the magnitude relationship between the amplifier output and the reference voltage, the avalanche photodiode and the variable gain control amplifier that are controlled by the two differential pairs can be A variable gain #JO control circuit characterized by changing one of the control signals. the avalanche photodiode and a variable gain control amplifier to which the output of the photodiode is applied; the output of the amplifier is input to a signal identification device and fed back to the avalanche photodiode and the variable gain control amplifier, and the multiplication factor and gain are individually determined. In a variable gain control circuit for an optical signal, one of the transistors 7j of the two differential pairs Ym is connected in common, and depending on the magnitude relationship between the amplifier output and the reference voltage, either A variable gain characterized in that by varying the current flowing through one differential pair VC, the control signal to the avalanchef odd diode and the variable +ui control amplifier obtained from the two differential pairs is changed. control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13877082A JPS5928710A (en) | 1982-08-10 | 1982-08-10 | Variable gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13877082A JPS5928710A (en) | 1982-08-10 | 1982-08-10 | Variable gain control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5928710A true JPS5928710A (en) | 1984-02-15 |
| JPH0336324B2 JPH0336324B2 (en) | 1991-05-31 |
Family
ID=15229786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13877082A Granted JPS5928710A (en) | 1982-08-10 | 1982-08-10 | Variable gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5928710A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61114610A (en) * | 1984-11-08 | 1986-06-02 | Mitsubishi Electric Corp | Dc amplifier with automatic gain control |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5158850A (en) * | 1974-11-20 | 1976-05-22 | Hitachi Ltd | Hikaritsushinyo agc hoshiki |
-
1982
- 1982-08-10 JP JP13877082A patent/JPS5928710A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5158850A (en) * | 1974-11-20 | 1976-05-22 | Hitachi Ltd | Hikaritsushinyo agc hoshiki |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61114610A (en) * | 1984-11-08 | 1986-06-02 | Mitsubishi Electric Corp | Dc amplifier with automatic gain control |
| JPH0356482B2 (en) * | 1984-11-08 | 1991-08-28 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0336324B2 (en) | 1991-05-31 |
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