JPS5928064B2 - Bias charge formation method in charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming bias charges in a charge transfer device, and particularly to a method for shading bias charges by keeping the amount of bias charges constant in a photoelectric conversion section of a solid-state imaging device using a two-dimensional charge transfer device. and methods for reducing false signals.

A CCD (Charge Couple) is used as a charge transfer device.
dDevice) and BBD (BucketBrigad)
eDevice) is known as a representative one,
Furthermore, as an imaging method for an imaging device using this CCD, a method called a frame transfer method is known.

The most important characteristic of the above-mentioned device is the efficiency of signal charge transfer. This is due to the fact that signal charges proportional to the optical image stored in potential wells below the transfer electrodes are outputted via different numbers of transfer electrodes. Further, even when the signal charge to be transferred is small, the transfer efficiency is low, and it is difficult to transfer minute charges in a charge transfer element. In other words, if the transfer efficiency in a two-dimensional charge transfer element is poor, (c) resolution and uniformity of resolution within the screen will be poor. (2) Shading will appear within the screen.

(3) Imaging cannot be performed with a small amount of input light. This may cause the quality of the screen to deteriorate. To improve this transfer efficiency,
A method of injecting bias charge called fat zero is well known.

FIG. 1 is an example of the effect of vertical resolution improvement by bias charge, which was experimented by the inventor. The experiment is 512 (ri) x 340
This was performed using a round pixel frame transfer CCD, and the amount of bias charge injected was 200 nA, which is 20% of the saturated light amount! In addition, the input light amount is 100n, which is 1/10 of the saturated light amount.
I gave it an A. In FIG. 1, the dotted line shows the case without bias charge, and the solid line shows the case with bias charge. As is clear from this figure, significant resolution improvement can be obtained by bias charge injection. Experiments have also shown that uniformity of resolution depending on screen position, shading, and imaging with small input light are improved. There are two methods for injecting this bias charge: optical and electrical. The optical method forms a fat zero by irradiating the CCD photosensitive area with noq light whose intensity does not change over time. Usually, a red LED, which is easy to handle, is used for this bias light. However, this method makes it difficult to irradiate the entire surface of the photosensitive area with bias light with a uniform intensity, requires a special optical system, runs counter to the desire for miniaturization of solid-state imaging devices, and also reduces power consumption and aging. Change and price were also problems. On the other hand, an electrical method involves injecting bias charges into each column of the CCD from a PN junction. In this method, an input diode and an input gate electrode are provided at one end of the CCD photosensitive section, and a constant bias charge is constantly injected. However, the conventional electrical bias charge injection method for improving vertical transfer efficiency has the following drawbacks. In other words, the threshold voltage V depends on the location of the input diode and input gate.
The unevenness in th becomes unevenness in the amount of bias charge injected, and white vertical lines appear on the screen. The absolute value of the bias charge amount differs depending on the length of the transfer. Therefore, as shown in FIG. 2a, shading of the bias charge amount appears in the output between the input gate side and the storage section side.
To overcome this drawback, Japanese Patent Application Laid-Open No. 54-68
The technique disclosed in Japanese Patent No. 190 is useful.

This relates to a two-dimensional charge transfer device and its driving method. After injecting a sufficient amount of bias charge from the input gate, the input gate voltage is set to a predetermined value so that a certain amount of bias charge remains in the potential well. In this method, the excess charge is returned to the input diffusion layer side through the input gate. However, even with this method, it is difficult to completely eliminate vertical lines and vertical shading.
This is because when the input gate voltage is set to a predetermined value in order to have a certain amount of charge remaining in the potential well, if the gate voltage setting differs from place to place, the remaining bias charge will also be uneven, resulting in Vertical stripes appear. In addition, as another solution,
There is a technique disclosed in Publication No. 32. This is related to the drive method of the charge transfer device, in which a voltage is applied to reduce the amount of bias charge in each potential well during the period before the photoaccumulation pulse is applied to the photosensitive area of the CCD, and a constant amount of bias is applied to the potential well. This means that a charge remains. This method significantly improves vertical streaks.

However, there is a drawback that vertical shading as shown in FIG. 2b newly occurs. This is because when the potential well is pushed up and a certain amount of charge remains in order to reduce the bias charge, the charge pushed up by the push-up operation flows toward the input gate and storage section, causing the input gate, The amount of bias charge near the storage section becomes small, resulting in shading. Vertical streak-like unevenness and shedding in the amount of bias charge are particularly noticeable when driving with a low signal current of 1, which is performed to increase the sensitivity of the imaging device, so there is a demand to keep this amount even smaller than in the past. FIG. 2c shows a desirable bias charge amount distribution.

The present invention has been made in view of the above points, and provides a method for improving the electrical bias charge injection method, allowing bias charges to remain evenly, and eliminating the occurrence of vertical stripes and shading. The purpose of this invention is to improve the signal-to-noise ratio and obtain an imaging device with high sensitivity.This invention uses a potential well to determine the amount of bias charge during the period between the transfer operation of the charge transfer element and the optical storage operation. By pushing up and accumulating a predetermined number of electrodes of the input gate, storage section, or photosensitive section during this pushing up period, the bias charge amount distribution within the potential well is made uniform.

The system of the present invention will be explained below with reference to the drawings. Figure 3a shows a frame transfer method CCD for explaining the method of the present invention.
In the cross-sectional view, 1 is the bias charge injection position, 2 is the photosensitive part, and 3 is the photosensitive part.
is the storage section.

This figure simply shows the case of four-phase drive consisting of two layers of polysilicon electrodes. Transfer electrode φ11, φ
12, φ13, φ4, φSl, φS2, φS3, φS4
4-phase clock pulses with a 90° phase shift are applied to the 4-phase clock pulses.

Under the insulating layer 4 such as SiO2 is a P-type silicon substrate 5, and a negative DC voltage 6 is applied to this substrate so that a depletion layer is always formed during the transfer period to improve transfer efficiency. First, during the frame transfer period, as shown in FIG. 3B, a large amount of bias charge is injected under the transfer electrode of the photosensitive section 2 from the input diode IS by opening the input gate G1.

The hatched area in FIG. 3b is the uneven bias charge injected. Next, each electrode of the photosensitive section is uniformly set to a high voltage, and at the same time, the input gate G1 and the storage section 3 are φS3 and φS.
Apply a low voltage such that 4 is an accumulation voltage to guard against bias charge leakage.

As shown in FIG. 3c, φ11, φ12, φ1 of the photosensitive section 2
Since all four electrodes 3 and φ14 have a uniformly high voltage, bias charge unevenness in the transfer direction is eliminated. Then, as shown in FIG. 3d, the input gate G1 and the storage section 3 are kept in the accumulation state, and the photosensitive section 4 is
When the electrodes are simultaneously brought to a low voltage, the potential well is pushed up and a portion of the charge stored in FIGS. 3b to 3c overflows from the potential well.

The overflowing charges are then recombined on the silicon substrate 5. As a result, an even and uniform bias charge remains in the potential well. Next, if a high voltage is applied to φ,, φ12, and an even lower voltage is applied to φ13, φ4, φ3, φ4
The charges under the electrodes are distributed under the adjacent electrodes φ11 and φ2, and as shown in FIG. 3e, equal amounts of bias charges are formed under the electrodes φ11 and φ2.

Thereafter, light accumulation for photoelectric conversion is performed. FIG. 4 shows voltage waveforms applied to the bias charge injection section 1, photosensitive section 2, and storage section 3 in order to realize the change in the potential well shown in FIG.

This operation must be performed within the vertical blanking period. In the frame transfer period A, first the input gate G1
A high voltage is applied to open the gate, and sufficient charges are stored in φ and φI of the photosensitive section 3.

Next, in period B, the four electrodes of the photosensitive section 3 are uniformly applied to a high voltage to eliminate charge unevenness in the transfer direction. At this time, the voltages of the input gate G1 and the storage portions φS3 and φS4 are lowered to a voltage at which accumulation occurs to enhance the guard effect. (Accumulation occurs when the voltage drops below the level indicated by the dotted line 7 in FIG. The excess charge spills out of the potential well into the substrate and is dissipated by recombination. At this time, input gate G1 and storage section φS3,
It is important to keep the guard of φS4 at period C. (In Figure 4 J and k, accumulation occurs when the voltage falls below the level indicated by dotted lines 8 and 9.) After that, φ11 and φ12 are set to high voltages, and φ13 and φ14 are set to high voltages.
is set to a lower voltage to leave an equal amount of bias charge only below φ and φ1. In this method, periods A, B,
The total number of C must be completed within a vertical blanking time of 1250 μS.

First, the setting of period A is determined by the product of the frame transfer frequency time and the number of frame transfers. The inventor's experiments have revealed that in the case of the above-mentioned 512()×34O(H) pixel frame transfer type CCD, there is no resolution deterioration even when the frame transfer frequency is set to 500 KHz. Therefore, period A is 2 μS x 256 times = 5
It becomes 12 μS. Next, period B can be set to 1 clock of the frame transfer frequency, but considering the stability of operation, it is set to 50 μm.
Let it be S. The setting of the push-up period C depends on the time constant required for recombining excess charges, and this time constant is 500 μm.
It has been found from experimental values that it is sufficient if it is S or more. Therefore, the total of periods A, B, and C is A: 512 μS + B: 50
μS+C: 500μS=1062μS. Since this value is smaller than the vertical blanking period of 1250 ItS, it can be realized by this method. Control of the amount of bias charge in this method is obtained by boosting voltage Vbc.

In FIGS. 3 and 4, charges are left only under φI and φ, but it goes without saying that in the next field, charges are left only under φ13 and φ14. As explained above, the present invention stores charge in excess of the required amount in advance in a potential well, and then pushes up the potential well while at the same time preventing excess charge from flowing to the input gate side and the storage section side. All charges are discarded by recombination with the substrate, and the charges remaining in the potential well as a result of being pushed up are used as bias charges.

Therefore, according to the present invention, by pushing up the potential well and causing excess bias charge to overflow, the amount of charge under each electrode can be made uniform evenly. Therefore, problems such as vertical stripes and shading caused by bias charge unevenness are solved, and even with a small amount of input light, an output image with a good S/N ratio can be obtained and high sensitivity of the solid-state imaging device can be achieved. Further, according to the present invention, frame transfer method C
It also has the effect of significantly reducing vertical smear (also called superpause phenomenon) that occurs in CDs.

The present invention is not limited to the above embodiments.

Figures 5 and 6 show other embodiments of the present invention, with Figure 5 showing the relationship between potential wells and bias charges, and Figure 6 showing voltage pulses for four-phase drive in the case shown in Figure 5. . This method is carried out in Figs. 3 and 4, and the input gate G1
Instead of using the accumulation section for the charge push-up period to prevent charge outflow, the two arbitrary transfer electrodes (φI and φI in the case of FIG. 5) of the photosensitive section 2 are used for the charge push-up period. This is a method to efficiently recombine excess charges with holes by accumulating them. The operation of this method will be explained. First, charge is input by opening the input gate and injecting a large amount of charge in the same way as the method shown in FIG. A voltage of 12 VbC is applied to φI and φ so that the required amount of bias charge is obtained.

At that time, φ13 and φ4 apply voltages that result in an accumulation state. Therefore, the excess charge flows to the adjacent electrode in the accumulation state and recombines with the hole, leaving a uniform bias charge under the electrode to which Vbc is applied. Next, φ11 for normal optical storage operation.
, φ12 are given a voltage higher than VbC, φ13, φ1
4 remains the accumulation ratio. FIG. 6 shows voltages or clock pulses applied to each electrode to realize this operation. (Dotted lines 10 and 11 in this figure E and f
Accumulation occurs below the level of . ) In this method, input gate G1 and storage section 3 as shown in FIG.
This has the advantage that there is no need to guard the input gate G1, and it is sufficient to simply apply a DC bias to the input gate G1. However, it has been confirmed through experiments that the shading is worse than the method described in FIGS. 3 and 4. Further, as a modification of FIGS. 5 and 6, there is also a method shown in FIGS. 7 and 8 in which one electrode of the photosensitive section 2 is pushed up during an accumulation period.

FIG. 7 shows changes in the potential well, and FIG. 8 shows drive waveforms for realizing FIG. 7. This operation is shown in Figure 5.
This can be achieved in the same way as in Figure 6. In Figures 5 and 6, the residual bias charge electrodes are φ11 and φ12, but this combination is (φ13, φ4), (φ1, φ3), (φ2, φ4
), (φ1, φ4), and (φ2, φ13), and the same effect can be expected in any case.

In addition, the residual bias charge electrode in FIGS. 7 and 8 is φ1
, φ2, φ1, but this combination is (φI,・φ1
3, φ14) (φ11, φ13, φ14) are considered, similar effects can be expected.

It goes without saying that the same effect can also be obtained by storing bias charges in one electrode of the photosensitive section and using the other three electrodes as storage. In addition, in the previous explanation, input of bias charges was carried out by opening input gate G1 during the frame transfer period, but another method is to open input gate G1 during the period shown in FIG. 4B and input bias charges. Also good.

Furthermore, instead of opening and closing the input gate, the input diode S
It is clear that the bias charge may be input by changing the operating point of the . Further, the voltage Vbc that determines the amount of bias charge is not fixed to a constant value, but may be applied in a stepwise manner from a high voltage to a low voltage Vbc. Alternatively, a high voltage and a low voltage Vbc may be applied in a pulsed manner, or a low voltage may be applied a little higher than Vbc in the initial period of the pulse, and the voltage may be gradually increased to Vbc. Further, in order to obtain an accumulation state, the substrate voltage may be made positive during the period when Vbc is applied.

The above embodiments and modifications were explained using the surface channel type, but
It is obvious that the present invention can be applied to a buried channel type as well as an interline type.
The present invention is applicable not only to CDs but also to bias charge forming methods for various charge transfer devices used in solid-state imaging devices.

[Brief explanation of drawings]

FIG. 1 shows the vertical resolution characteristics of a two-dimensional charge transfer element, and is an example of improved characteristics when bias charges are added.

Claims (1)

[Claims] 1. In a charge transfer element in which a plurality of transfer electrodes are formed on a semiconductor substrate via an insulating layer, a voltage applied to the input gate electrode of the bias charge injection section before applying a photoaccumulation pulse to the transfer electrodes. to electrically inject a bias charge in excess of the necessary amount into the potential well under the transfer electrode, and then push up the bottom of the potential well and at the same time inject a predetermined electrode of the input gate electrode or the transfer electrode. By setting the accumulation state, the excess bias charge is substantially not returned to the bias charge injection part, but overflows into the substrate, and then the remaining bias charge is equally distributed to the potential well under the transfer electrode where photoaccumulation is performed. A method for forming bias charges in a charge transmission element, characterized in that: