JPS5927681A - Convergence circuit for television receiver - Google Patents

Abstract

PURPOSE:To reduce adjusting stages at the end of installation and assembling, by writing a expected reference data in an idle memory area of an ROM for controlling a CPU and writing only an error with the reference data to a frame memory at the initial adjustment. CONSTITUTION:The amount of shift in expectable convergence is written in the idle area 22a of an ROM 22 in advance, an adjusting keyboard 26 is operated at the initial adjustment of convergence and transferred to a nonvolatile memory 24 via a CPU 21. The data of the memory 24 is fetched to the CPU 21 and a required interpolation calculation is performed, and transferred sequentially to the frame memory 17 as an actual correcting data. The rough correction data written in the memory 17 is read out with a signal from an address counter circuit 13 and applied as a correcting current to convergence coils 8-11 via a latch 18, a D/A converter 19 and an output circuit 20 for performing rough correction of the convergence.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a convergence circuit for a video projector, etc., and in order to achieve convergence matching based on convergence correction data digitally stored in a frame memory, and to perform memory backup when the power is cut off, etc. This relates to a digital convergence circuit equipped with a backup memory for backing up the convergence correction data, and in particular, standard data predicted in principle is written in a free memory area of a CPU control ROM, etc., and this standard is used during initial adjustment. The frame memory modification writes only the error with the data into the nonvolatile memory, thereby greatly shortening the adjustment process at the time of installation or assembly completion.

A plurality of high-intensity cathode ray tubes (hereinafter referred to as CRTs) each emitting colored light corresponding to the three primary colors are used.

A video projector that enlarges and projects the image of each Cf ('I') onto a screen using a projection optical system, etc.
etc., a convergence circuit is required to superimpose the images of green G) and stomach IB+ on the screen. Conventional convergence circuits are horizontal.

A parabolic wave obtained by waveform shaping a vertically polarized wave signal,
After synthesizing the sawtooth wave signals and amplifying the current, the CRT
A method was adopted in which the color images were converged by being supplied to a convergence yoke attached to the neck of the camera. However, when correction is performed using a signal obtained by waveform shaping in this manner, there is a problem in correction accuracy, which becomes more noticeable as the screen size increases.

Taking these points into consideration, a method called digital convergence has been proposed as a method of obtaining accurate comparison over the entire screen.

Simply put, this method divides the screen into an arbitrary number of grid-like blocks and digitally stores convergence correction data for each grid point in frame memory in order to perform highly accurate correction over the entire screen. Then, after reading out this data in synchronization with beam scanning and converting it from D to A,
The output of the current is guided to the convergence yoke as a correction current to perform convergence correction.

An outline of this method will be explained below with reference to FIG.

In this block diagram, il+ typically represents a luminance and chroma signal processing circuit, and the way it is synthesized is (, R
It is added to the cathode of T121 and images are displayed as appropriate. (
3) shows a vertical and horizontal deflection circuit, the output of which is supplied to a deflection coil (4) to control the deflection of the electron beam as usual. (5) is a frame memory in which the convergence correction data of each lattice point of the crosshatch pattern displayed on the screen by the output of the crosshatch pattern generator (6) is stored in the form of a digital correction data signal. is memorized.

The horizontal deflection pulse signal and the vertical deflection pulse signal of the deflection circuit 13) correspond to the line mark and the line IVI, respectively.
7 to the °C address counter circuit (7),
It is converted into an address signal corresponding to scanning.

The output address from the address counter circuit (7) is
'C frame memory (5) via multiplexer (8)
are sequentially added as address inputs. The addresses of the memory portions of the frame memory (5) that store digital data to be successively output are sequentially designated by a CPU (central processing unit) (9). Then, based on this address signal, a digital correction data signal is read out from the memory (51) to the latch circuit side.

The digital correction data signal temporarily latched by the latch circuit (101) is converted into an analog signal by a digital-to-analog converter ton=, and is applied as an input to the output circuit 0?.The output circuit o21 is connected to each analog The correction data signal is current-amplified to form a convergence correction current.The output circuit 021's power (convergence correction current) is connected to the convergence field (131) with an IJ attached to the neck of the CRT (2). It is supplied to a convergence coil and the deviation of one side is corrected.

By the way, when the power is cut off, the frame memo 9 (
However, the stored comparance correction data will be erased, so this is a countermeasure. is provided and stores all convergence correction data in the frame memory (5) as a backup.

The frame memory (5) must respond immediately when read under the control of the CPU f9+, and it is difficult to configure the frame memory (5) with a non-volatile memory with a very long access time. A non-volatile memory (14a) is provided to form a backup memory to back up the memory (5), and when the power is cut off, each convergence correction data 7 is stored in the non-volatile memory (14a). °C
I'll leave it there. Then, when the power is turned on, CPUt9
Non-volatile memo via address bus Buddha) from 1! J(1
4a), an address signal for specifying each address of the memory (14a3) is output in parallel, and each convergence correction data is read out according to the address signal, and at the same time processing such as interpolation is performed by the CPU 191. , in the database tt+IY-C frame memory (5).

Make sure that each compass supplementary data that has been read is written in.Next, press the operation keyboard (15+).
By adjusting the convergence of the frame memory (5
) When each convergence correction data of
A crosshatch pattern is formed and displayed on the CFtTi 21.

Note that the crosshatch pattern signal outputted from the crosshatch pattern generator (6) to the video amplifier circuit (11) is formed based on the output signal of the address counter circuit ('2), and the crosshatch pattern signal is generated based on the output signal of the address counter circuit ('2).
When the screen of 'I' 121 is divided into an arbitrary number of grid blocks, that is, MxN grid blocks, and the convergence is good, the shift of the crosshatch pattern is corrected over the entire screen of CR'1'i21.

Also, when adjusting the convergence, the marker generator 06
・No・7-Car signal passes through the video amplification circuit ([) to Cl
(A mark is displayed on the screen of the CRT 12+ to indicate the grid point where the convergence correction data is to be extracted. Move to the vicinity of the grid point to be changed. Note that the marker generator 06)
The marker signal output from the address counter circuit (7) is formed based on the output signal of the address counter circuit (7).

Therefore, when adjusting convergence, operate the keyboard (151) and input/output interface (17a) to L-CCP U (9++ knee, CFt
A movement control signal for the mark displayed on the Ti 21 is output, the mark is moved near a grid point on the crosshatch pattern where the convergence shift is significant, and the CPU 191 is commanded to reconsider the convergence.・After moving 7-ri, operate keyboard 051 and press keyboard l.
l5) to input/output interface (17a)
(One person output interface (17a) that outputs the convergence correction data signal for W switching to the CPU 191.
The CPU 191C reads the convergence correction data 1 via the CPU 191C and writes convergence correction data for rewriting into -tt°C7L'-A/-f-li (5), thereby rewriting the convergence correction data in the frame memory (5).

However, in the case of the digital convergence circuit mentioned above, non-volatile memo! The address of J (14a) is specified by a parallel address signal via the address bus IA) and the address of the non-volatile memory (14a) is specified via the data bus 1.
Each convergence correction data is input in parallel to , and each convergence correction data is output in parallel from the nonvolatile memory (141!L) to data bus 1, reducing the access time of the nonvolatile memory (14a) by the CPU 191. On the other hand, non-volatile memo 9C1
4a) It is necessary to provide multiple input and output terminals for non-volatile memo! J (14a) has the disadvantage that the number of terminals increases and the size increases, and that the space required for installation becomes large. In addition, the CPU 191 has one memory (5),
Needless to say, the rewrite control section (14a) also functions as °C.

Also, in such a convergence circuit, the non-volatile memo! Since random data is written in +(14a), it is necessary to adjust each crosshatch point individually, and this adjustment takes a long time.

This invention was made with the above points in mind,
Regarding the former drawback, there is a frame memory that digitally stores the convergence correction data for each grid point of the crosshatch pattern for convergence adjustment, and a frame memory that digitally stores the convergence correction data for each grid point of the crosshatch pattern for convergence adjustment, and a frame memory that digitally stores the convergence correction data for each grid point of the crosshatch pattern for convergence adjustment. A digital convergence circuit that includes a backup memory for backup storage and a rewriting control unit that controls rewriting of both memories, and reads out the convergence correction data from the frame memory in synchronization with convergence adjustment 1: screen scanning. The backup memory is formed by a nonvolatile memory having one input/output terminal into which address signals for specifying each of the addresses and convergence correction data for writing are input, and outputting read convergence correction data. With.

The rewriting control unit serially converts the address signal and the convergence correction data for writing, outputs it to the input/output terminal, and parallel converts the convergence correction data for reading output from the input/output terminal. Provide an input/output interface to
The rewrite control unit may time-divisionally control the input of the address signal and the writing convergence correction data to the input/output terminal, and the output of the reconvergence correction data read from the input/output terminal. , regarding the latter's shortcomings.

F in CPU f91 (in the memory empty area of OM,
This is intended to solve the problem of -C by taking a configuration in which standard digital convergence data is taken into consideration, read out at the time of initial adjustment, and written into the nonvolatile memory (14a). Details of the present invention below - 1 yen: 2nd
An example of the figure will be explained.

In FIG. 2, the same symbols as in FIG. 1 indicate the same things, and the difference is that instead of the nonvolatile memory (14a) in FIG. 1, there is a nonvolatile memory 9 having one input/output terminal P).
(1, ib) are provided, and input/output terminals IPJ Y, tJ
'r Input/output interface (17b) I provided in place of the human output interface (17a) in Figure 1:
The connected point and ROMIXj& for the program memory of the CPU 191 are points where an attached ROM (Jl) is added. , Note that the input/output interface (1
An operating keyboard 09 is also connected to 7b). Then, the address signal for specifying the address of the nonvolatile memory IJ (14b) outputted in parallel from the CPU 191 via the address bus (AIY) to the input/output interface (17b) is serially converted by the input/output interface (17b). An address signal is serially input to the input/output terminal IP+, and the non-volatile memory (1
4b) is addressed. Similarly, the data bus (D
Each convergence correction data for writing input by two people is transmitted via the input/output interface (17b).

It is serially converted by the input/output interface (17b), and each compar sense correction data for error input is serially input to the input/output terminal +P+, and is stored in the nonvolatile memory (14
Each convergence correction data is written in b). In addition, each convergence correction data read from the nonvolatile memory (14b) is serially output from the input/output terminal to the input/output interface (17b), and the input/output interface, 7 ace (17b), Terminal P1
Each convergence correction data inputted from is converted into parallel data and outputted as °C data path tAxi:. Then, the output of each convergence correction data of the address signal and write voltage to the C input/output terminal IP+, and the input/output terminal +Pl
The output of each convergence correction data from the input/output interface (17b) to \ is time-divisionally assisted by the CPU'U (91).By the way, when the power is turned on, from the nonvolatile memory (14b) to the frame memory (5), Although the time required to read out each convergence correction data is longer than in the conventional case and takes several seconds, there is no risk of any inconvenience since it takes several seconds before the screen starts to be displayed on the CRT+21.

Furthermore, in one aspect of the present invention, an empty area of the program ROλ4 section for the CPU 191 or an independent ROM+,! 1
Each crosshatch crossover predicted from the 11m design standard value +
- Write down the digital position of the standard correction convergence 1 in Ell and set it to 10 M at the time of initial adjustment.
(21 correction data is transferred to the non-volatile memory (14b), and the data is directly transferred to the frame memory (5). Then, under the control of CPU f!31, each (, Read RT, synchronize with the timing of horizontal deviation, read out °C, perform two consecutive D-A conversions, and obtain the convergence current ヲF'X -C, convergence q.
- 031, and the provisional convergence-corrected image is displayed on the screen.

Next, while looking at the lattice convergence situation of the image of screen L, especially the image with the crosshatch pattern superimposed, only °C is used for areas with large errors, that is, convergence correction data corresponding to the deviation unique to that set. only,
-H volatile memory (14b) or frame memory (
5) Immersed myself in Atonenos, which stores the data of the grid points to be corrected, and change the color. This operation is performed using the keyboard 6 above.
5) by manual operation.

3. On the screen from the above-mentioned Kashihatake corrected convergence absorption). The raster deviation of G and B primary color CRTs is
Depends on the relative positional relationship between T and the screen,
Once the arrangement of CF(T) and the position of the screen are determined, it can be predicted in advance.

Also, in the case of jfi ′, @CRT, the structure of the sulfur gun,
The required standard correction compliance can be predicted from data such as the dimensions up to the fluorescent surface, the characteristics of the deflection yoke, and its mounting position.

According to the present invention, one input/output terminal of the nonvolatile memory is commonly used for inputting an address signal, inputting convergence correction data for arranging, and outputting read convergence correction data, Significantly reduces the number of non-volatile memories that form the back-up memory.
In addition to being able to be converted into JX type, non-volatile memory [
There is no need to connect a near address path or data bus, and the installation space can be reduced. or,
At the time of initial adjustment, the time required for J adjustment is also significantly shortened (2) because standard data is transferred from the ROM under volatile memory (2).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the prior art of this type of circuit, and the second factor is a block diagram of the con/<-sensing circuit of the present invention. (5) Frame memory (14b) Non-volatile memory
+91cPU 121 (211ROM
(17b) Amendment to Input/Output Interface Procedures (Spontaneous) To July 8Q, 1988 To the Commissioner of the Japan Patent Office 1. Indication of the case 1982 Patent Application No. 137036 2. Name of the invention Convergence of three-tube video projector Correction circuit 6
, Patent applicant address: 2-18, Keihan Hondori, Moriguchi City Name (188) Sanyo Electric Co., Ltd. Representative: Kaoru Iue 4, Agent address: 2-18-5, Keihan Hondori, Moriguchi City, Subject of amendment 0 Application 1 and the “Title of the Invention” column of the specification. O The full text of the specification and "Figure 1" and "Figure 2" of the drawings. 6. Contents of the amendment 0 The "title of the invention" that should have been in the document and specification is amended to read "convergence of three-tube video projector. 0 The specification and drawings are amended as shown in the attached sheet. Document 1, Title of the Invention Convergence correction circuit for three-tube video projector 2, Claims + 11 A digital device that is the same as a frame memory that stores convergence correction data at each grid point of a crosshatch pattern assumed on the image plane as a digital value. A non-volatile backup memory that stores values is read out in synchronization with screen scanning, and the D-
In a circuit that performs convergence correction on the screen using Ai conversion high output, standard convergence correction data predicted such as the placement conditions of each CRT is written in advance to ROM, and the data in the ROM is transferred to the non-volatile memory at the time of initial adjustment. The data is transferred to the memory, initial convergence correction is performed based on this transferred data, and after that, among the data in the frame memory, only the error from the standard value of the compherence correction data at the lattice points is changed. 1. A convergence correction circuit for a three-tube video projector, characterized by the following configuration: (2) The compar sense correction circuit for a three-tube video projector according to claim 1, wherein an empty memory area of the ROM is used as the ROM for sending a control program to the CPU. 3. Detailed Description of the Invention In order to match the convergence based on the stored convergence correction data and to perform memory backup in case of power cut-off, etc., it is predicted in principle that the convergence correction data is stored as a backup projector. The reference data is written in a free memory area of the CPU control ROM, etc., and at the time of initial adjustment, only the error with this reference data is introduced into the frame memory or the non-volatile memory. This is intended to significantly shorten the adjustment process. A video projector uses a plurality of high-intensity cathode ray tubes (hereinafter referred to as CRTs) each emitting colored light corresponding to the three primary colors, and uses a projection optical system to enlarge and project the image of each CRT onto a screen. A convergence circuit is essential to superimpose the red (R), green (G), and evening (B) images on the screen. Conventional convergence circuits synthesize parabolic and sawtooth waveform signals obtained by waveform-shaping horizontal and vertically polarized wave signals, amplify the current, and then use a compass attached to the neck of the CRT to shape the waveforms in this way. When correction is performed using the signals obtained in the above, there is a problem in correction accuracy, which becomes more noticeable as the projection screen size increases. Taking these points into consideration, a method called digital convergence has been proposed as a method of obtaining highly accurate convergence across the entire screen. Simply put, this method divides the screen into an arbitrary number of grid-like blocks and stores convergence correction data for each grid point in a frame memory digitally in order to perform highly accurate correction over the entire screen. , This data is read out in synchronization with beam scanning, and after D-A conversion,
The output is guided to the convergence yoke as a supplementary current to perform convergence correction. The details of the compensating circuit of the three-tube projection video projector of the present invention will be explained below with reference to FIG. This will be explained with reference to. In this block diagram, fl) represents a luminance and chroma signal processing circuit to be input to each CRT, and its output is applied to the cathode of the CRT (2R, 2G, 2B) to display images as appropriate. (12) shows the vertical and horizontal deflection circuits, whose outputs are the deflection coils A/(3R,
3G, 3B) and control the deflection of the electron beam like a falcon. (17) is a frame memory in which convergence correction data for each grid point of the crosshatch pattern displayed on the screen by the output of the crosshatch pattern generator 04) is stored in the form of a digital correction data signal. be done. The horizontal deflection pulse signal of the deflection circuit 0 and the vertical deflection pulse signal 1
The direction pulse signals are input to the address counter circuit (+3) via the fin (H) and line connections, respectively.
It is converted into an address signal corresponding to scanning. The output address from the address counter circuit (13) is
The frame memory (
+7) as address inputs. and,
Based on this address signal, digital/V correction data signals are sequentially sent out from the memory (17) to the latch circuit α8). The digital correction data signal temporarily latched by the latch circuit θ~ is transferred to the digital-to-analog converter θ9)
It is converted into an analog signal by D) and applied as an input to the output port i. The output circuit (20) current amplifies each analog correction data signal to form a convergence correction current. The output (compensance correction current) of this output circuit (η) is from the CRT (2R, 2
B) Vertical convergence coil attached to
8Hto) and horizontal square =≠curvature are corrected. By the way, when the power is cut off, the frame memory (l
Since each convergence correction data digitally stored in η will be erased, a backup memory (non-volatile memory 24) is provided to back up the frame memory (17), and each convergence correction data stored in the frame memory αη will be deleted. Save the convergence correction data as a backup. The frame memory (+7) must immediately respond to readout by the address signal from the address counter circuit 03), and the frame memory Q7)
It is difficult to represent this in non-volatile memory, which has a very long access time. Therefore, in order to back up the frame memory (+7), a non-volatile memory forming a backup memory is provided, and when the power is cut off, @J stores each convergence correction data as a backup in the non-volatile memory. I'll keep it that way. When the power is turned on, an address signal for specifying each address of the memory (24) is sent from the CIi'U (211 to the nonvolatile memory (241) via the nonvolatile memory IJ (24) and the interface circuit). Each convergence correction data is output and read out according to the address signal, and at the same time, the CPU (211) performs processing such as interpolation. Make sure that the correction data is falsified.Next, use the operation keyboard (2
When each convergence correction data in the frame memory θη is replaced by the convergence adjustment operation in step 61,
That is, during convergence adjustment, the crosshatch pattern signal from the crosshatch pattern generator 04) is sent to the CRT C2R, 2G, 2B) via the video amplifier circuit +1).
A crosshatch pattern signal is output from the crosshatch pattern generator θ4) to the video amplification circuit (1), and a crosshatch pattern is formed and displayed on the screen (3o). It is formed based on the output signal of In some cases, misalignment of the crosshatch pattern is corrected across the entire screen of the example screen. Also, when adjusting convergence, the marker generator)
The marker signal is sent to the CRTC via the video amplification circuit (11).
2R, 2G, 2B), and a mark is displayed on the screen to indicate the grid point where the convergence correction data is to be rewritten.The displayed mark can also be rewritten by operating the keyboard. Move to the vicinity of the grid point. In addition, a marker generator (16
) is formed based on the output signal from the address counter circuit end. Therefore, when adjusting convergence, use the keyboard (26)
outputs a movement control signal for the mark displayed on the screen upside down from the keyboard to the CPU (21) via the l/IO depot, and detects grid points with significant convergence deviations on the crosshatch pattern. Move the mark to the vicinity and put the convergence self 8 master r1i on CPUC211
After moving the Shikaku mark on Juru 0, operate the keyboard group and select I'10 boat (to) from the keyboard (26).
A convergence correction command signal is output to the CPU (211) via the CPU (211), and the convergence correction data sent via the I10 board is read by the CPU (21J) to create a convergence correction table for frame memory KiJ replacement.
The convergence correction data in the frame memory is also replaced. However, in such a convergence circuit in the prior art, since random data is written in the non-volatile memory for the initial adjustment, individual adjustment is required at each cross-noise point, and this adjustment requires The disadvantage is that it takes a long time. The present invention has been made in order to solve such problems that are unavoidable in the prior art, and is characterized by the standard digital convergence correction that is predicted in advance in the memory empty area in the ROM (22). The main feature is that data is brought in, read out at the time of initial adjustment, and brought into the non-volatile memory J+I.The details are shown below with rasters of the R, G, and B primary colors on the screen. The explanation will be explained with reference to Fig. 2. Fig. 2 schematically shows the misalignment of R, G, and B color raster patterns on the screen when no convergence correction is performed in a three-tube infin type video projector. 30R, 30G, and 30B indicate the raster patterns corresponding to the respective colors R, G.B. Generally, in the case of a 3CRT type projector, CRT"
The convergence deviation due to the arrangement of the CRT and the convergence deviation due to other causes are dominant.The convergence deviation due to the CRT arrangement is dominant. The convergence shift due to the CRT placement is C
Once the positional relationship between RT and the lens screen is determined, it can be predicted in advance. In the present invention, the amount of such predictable convergence deviation is determined in advance by storing ROM (23 free areas (2
2a), etc., and operate the adjustment keyboard during the initial adjustment of the comperience, and write it in this ROM (2a).
After the correction cheater written in 2) is imported and necessary interpolation calculations are performed, it is sequentially transferred to the frame memory (lη) as actual correction data.The approximate correction data written in the above frame memory 07 is read out by the address signal generated by the address counter circuit 03), and the latch (18)-D
A converter 09) - CRT (2R
) (Dli convergence yoke (8), horizontal convergence yoke (9), vertical convergence yoke 1101 of CRT (2B), and horizontal convergence yoke (11) are supplied as a correction current, and approximate correction of convergence is performed. As mentioned above, the convergence adjustment can be performed for each lattice point by operating the adjustment keyboard (26).According to the present invention, the initial convergence adjustment, especially the rough correction of the theoretical value, has already been made. Since only the detailed adjustments need to be made using the adjustment keyboard (26), the time required for one adjustment is greatly reduced.Furthermore, predictable deviations can be
This is a geometric shift caused by the positional relationship of the T-screen, and it is possible to significantly compress the Chigu. Therefore, the present invention can be realized simply by using the empty area ROM (22a) of the program ROM, and is very effective without requiring the addition of a new circuit. 4. Brief Description of the Drawings FIG. 1 is a block diagram of the circuit of the present invention, and FIG. 2 is an explanatory diagram of its operation. Snout...Frame memory, (2)...Non-volatile memory, (21)...CPU, cutting...ROM, hat...l
IO boat, (2R) (2G) (2B)...CRT
, +8)+91f101F11)... Compassennukoi di, (30)... Screen. Applicant Sanyo Electric Co., Ltd. 1T,-1,″\.

Claims (1)

[Claims] A non-volatile backup memory that stores the same digital values as a frame memory that stores convergence correction data at each lattice point of the assumed J-loss hatch pattern as a digital value. The contents of the frame memory are read out serially in synchronization with screen scanning from the programmed CPU, and the D-
In the circuit that performs "C" convergence correction on the A conversion output, standard convergence correction data predicted according to the design conditions of the receiver is written in the ROM, and at the time of initial adjustment, the data in the ROM is transferred to the frame memory, and this Perform initial convergence correction based on the transferred data,
From now on, among the data in the frame memory. A convergence circuit for a television receiver configured to rewrite and store only an error from a standard value of the convergence correction data at the lattice points. 21. The convergence circuit for a television receiver according to claim 1, wherein an empty memory area of the ROM is used for writing a control program into the CPU.