JPS5927612A - Amplifying circuit - Google Patents

Amplifying circuit

Info

Publication number
JPS5927612A
JPS5927612A JP13719582A JP13719582A JPS5927612A JP S5927612 A JPS5927612 A JP S5927612A JP 13719582 A JP13719582 A JP 13719582A JP 13719582 A JP13719582 A JP 13719582A JP S5927612 A JPS5927612 A JP S5927612A
Authority
JP
Japan
Prior art keywords
terminal
peaking
impedance
diode
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13719582A
Other languages
Japanese (ja)
Inventor
Yukio Akazawa
赤沢 幸雄
Noboru Ishihara
昇 石原
Mamoru Obara
小原 護
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13719582A priority Critical patent/JPS5927612A/en
Priority to CA000432581A priority patent/CA1201775A/en
Priority to US06/515,280 priority patent/US4542350A/en
Priority to EP83304191A priority patent/EP0101201B1/en
Priority to DE8383304191T priority patent/DE3381390D1/en
Publication of JPS5927612A publication Critical patent/JPS5927612A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G1/00Details of arrangements for controlling amplification
    • H03G1/0005Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0035Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements
    • H03G1/0052Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements using diodes

Abstract

PURPOSE:To attain stably a broad band, by providing an impedance adjusting circuit utilizing a differentiating resistor of a diode so as to adjust externally the peaking characteristics or the tuning characteristics. CONSTITUTION:A series feedback amplifying circuit having an input terminal 2 and an output terminal 4 is formed with an input transistor 6, a load resistor 7 and a series feedback resistor 8. Further, the impedance adjusting circuit 41 comprising a diode 22, a capacitor 9, and a constant current source 17 is connected between a high potential power supply terminal 1 and a low power supply terminal 2. The impedance of the adjusting circuit 41 is changed by a signal at a terminal 23. Since the gain of this amplifying circuit is expressed approximately with equation, the peaking characteristics are made variable by the signal at the terminal 23.

Description

【発明の詳細な説明】 本発明は、回路構成素子の素子値の修正、調整が困難な
モノリシック集積回路、ハイブリッド集積回路技術等に
おいて広帯域化のために用いられるピーキング特性ある
いは同調特性を有する増幅回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier circuit having peaking characteristics or tuning characteristics that is used for widening the band in monolithic integrated circuits, hybrid integrated circuit technologies, etc. in which it is difficult to modify or adjust the element values of circuit components. It is related to.

ピーキング形増幅回路を例りして従来技術について説明
する。第1図は、従来のエミッタビーキング増幅回路で
ある。回路構成は、人カドランジスタロと負荷抵抗7 
(R’LI) +直列帰還抵抗8CRp:1)及びピー
キングgJt9(Cp)よシなシ、3I′i入力端子、
4は出力端子である。この増幅回路は、直列帰還形増岬
回路であり、直列帰還抵抗8(REI)とピーキング容
nt9(Cp)の並列接続如よって、低周波領域では帰
還量が大きく、高周波領域では小さくなるように構成さ
れておシ、その電圧利得Avは、角周波数をω、ビーキ
ノグ答准9(Cp)を接続しないときの当該増幅回路の
3dB低下帯域をωbとして で近似される。
The prior art will be explained by taking a peaking type amplifier circuit as an example. FIG. 1 shows a conventional emitter beaking amplifier circuit. The circuit configuration consists of a human quadrant and a load resistance of 7.
(R'LI) + series feedback resistor 8CRp:1) and peaking gJt9 (Cp), 3I'i input terminal,
4 is an output terminal. This amplifier circuit is a series feedback type amplifier circuit, and the parallel connection of the series feedback resistor 8 (REI) and the peaking capacitor nt9 (Cp) makes the amount of feedback large in the low frequency region and small in the high frequency region. The voltage gain Av is approximated by ω being the angular frequency and ωb being the 3 dB lower band of the amplifier circuit when the Beekinog Answer 9 (Cp) is not connected.

従って、」二人よりω= 1 / (REI −Cp 
)のとき零点を生じ、この増幅回路の直列帰還抵抗8(
REI)とピーキング容量9(Cp)を適当な値に設定
することにより、入カドランジスタロ自身の狭帯域化効
果を補償することが可能であり、増幅回路の広帯域化を
図ることができる。
Therefore, ω = 1 / (REI −Cp
), a zero point occurs when the series feedback resistor 8 (
By setting the peaking capacitance 9 (REI) and the peaking capacitance 9 (Cp) to appropriate values, it is possible to compensate for the band narrowing effect of the input quadrant transistor itself, and it is possible to widen the band of the amplifier circuit.

第2図は、従来の差動形のエミッタピーキング増幅回路
である。第2図について説明する。回路構成は、前述し
た第1図のエミッタピーキング形増幅回路を差動形式と
したものであり、人カドランジスタロ、人カトラ/ジス
タ10.負荷抵抗7(RLI)I負荷抵抗15 (RL
2) 1直列帰還抵抗8(Rp:+)。
FIG. 2 shows a conventional differential emitter peaking amplifier circuit. FIG. 2 will be explained. The circuit configuration is a differential type of the emitter peaking type amplifier circuit shown in FIG. Load resistance 7 (RLI) I Load resistance 15 (RL
2) 1 series feedback resistor 8 (Rp:+).

直列帰還抵抗16(RE2)及び定′ル、波回路17に
より差動対が形成され、入カドランジスタロ及び人カド
が接続された(16成となっている。人力端f−は3−
1および3−2であり、出力端子は4−1および4−2
である。この増幅回路の動作は前述した第1図のエミッ
タピーキング形増幅回路と同様に考えられ、増幅回路の
電圧利得Avは人カドランジスタロ及びJOが同一であ
り、直列帰還抵抗8(1え月)と16(Rh;2)か等
しいとすると で近似される。
A differential pair is formed by the series feedback resistor 16 (RE2), a constant loop, and a wave circuit 17, and the input quadrant transistor and the input quadrant are connected (16 configurations.
1 and 3-2, and the output terminals are 4-1 and 4-2.
It is. The operation of this amplifier circuit is considered to be similar to the emitter peaking type amplifier circuit shown in FIG. is approximated by 16 (Rh; 2) or equal.

従っテ、前述の第1図のエミッタピーキング形増幅回路
の場合と同様に1直列帰還抵抗8(R,ρ。
Therefore, one series feedback resistor 8 (R, ρ.

16(RE2)及ヒヒーキノf’gM9 (Cp)k!
当;H+ffに設定することにより、置周波特性全袖イ
j(するピーキングを施すことが可能である。
16 (RE2) and Hihikino f'gM9 (Cp)k!
By setting H+ff, it is possible to perform peaking that improves the overall frequency characteristics.

以上説明したように、ピーキング技術は増幅回路の広帯
域化を施す上で有効な技術である。しかしながら、集積
回路等でピーキングを用いる場合、抵抗値及び容量値の
精度に限界があり、設計通りのピーキング特性を得る事
が困難である。特に高周波領域でのピーキングでは、直
列帰還抵抗とピーキング容量の積を小さくとる必要があ
るが、精度よく低抵抗値、低容量値を実現することがむ
ずかしく、場合によっては発掘を起す等の不都合が生じ
、設計通りにピーキングを施す事が困難である。また、
(1)式および(2)式で示したようにピーキングのた
めの極はCPとREIの積できする。利得および直流設
計からRElO値は決定されるので、ビーキング量の調
整はCpだけに左右されることになってし1い、ピーキ
ングを多くかけようとしてCpを大きくすると、極は低
周波111にずれこみ、低周波側で利得が持ちあがって
し1うという好捷しくない結果を生じる。これを避けよ
うとすると、ピーキングを十分かけることができなくな
り、ピーキングを有効に生かして広帯域化を図ることが
難しいという問題がある。
As explained above, the peaking technique is an effective technique for widening the band of an amplifier circuit. However, when peaking is used in integrated circuits and the like, there is a limit to the accuracy of resistance and capacitance values, making it difficult to obtain peaking characteristics as designed. Especially for peaking in the high frequency range, it is necessary to keep the product of the series feedback resistance and peaking capacitance small, but it is difficult to achieve low resistance and low capacitance values with high precision, and in some cases, it may cause inconveniences such as excavation. This makes it difficult to perform peaking as designed. Also,
As shown in equations (1) and (2), the peaking pole is the product of CP and REI. Since the REIO value is determined from the gain and DC design, the adjustment of the amount of peaking depends only on Cp. If you increase Cp in order to apply more peaking, the pole will shift to the lower frequency 111. This results in an undesirable result in which the gain is increased on the low frequency side. If an attempt is made to avoid this, there is a problem that peaking cannot be applied sufficiently and it is difficult to effectively utilize peaking to achieve a wide band.

ビーキング増幅回路を例として説明したが、一般的な同
調増幅回路においても同様であり、同様の問題がある。
Although the explanation has been given using a beaking amplifier circuit as an example, a general tuned amplifier circuit is also similar and has similar problems.

本発明は、これらのり(点を除去するために、集積化が
容易なダイオードの微分抵抗を利用したイノビーダンス
調整回路を具(#n L 、ピーキング特性あるいは同
調特性が外部端イから直流バイアス秀と独立に制御可能
なこ々を特徴とし、安定な広帯域化と製造のriii易
化をはかり低価格化することのできる増幅回路を提伊す
るものである。
In order to eliminate these glue points, the present invention includes an innovation adjustment circuit that uses diode differential resistance that is easy to integrate. The present invention proposes an amplifier circuit that is characterized by independently controllable components, and can achieve stable broadband operation, easy manufacturing, and low cost.

以1−’本発明の詳細な説明する。The following is a detailed explanation of the present invention.

第3図は、本発明の基本的なイノビーダンス調整回路の
実施例であって、■は高111:位電源端子、2は低電
位電源端子、21il−i信号入力端子、23はインピ
ーダンス調整入力端子、9はコツプ/す、22はダイオ
ード、17は′市流値口■変′屯流源である。又第3図
+blは動作を説明するための第3図+alの回路の交
流等価回路であり、CDはダイオード22の拡散容jt
、Rpはダイオード22の微分抵抗である。tb1図に
おいて端子21と低電位電源端子2間のインピーダンス
は次式で示すことができる。
FIG. 3 shows an embodiment of the basic innovidance adjustment circuit of the present invention, where ■ is a high potential power supply terminal, 2 is a low potential power supply terminal, 21il-i signal input terminal, and 23 is an impedance adjustment input terminal. , 9 is a droplet, 22 is a diode, and 17 is a source. Further, FIG. 3 +bl is an AC equivalent circuit of the circuit in FIG. 3 +al for explaining the operation, and CD is the diffusion capacitance jt of the diode 22.
, Rp is the differential resistance of the diode 22. In the tb1 diagram, the impedance between the terminal 21 and the low potential power supply terminal 2 can be expressed by the following equation.

RDとCDの積はダイオードのカットオフ周波数で決ま
る値であシ、動作電流IDによらず常に一定であるから
、(3)式のインピーダンスの周波数特性は抛4図のと
おりになる。即ちOとRD−CDで決まる極ω1.ω3
と、RD(Cp十Co)で決まる零点ω2を持つ。
The product of RD and CD is a value determined by the cutoff frequency of the diode and is always constant regardless of the operating current ID, so the frequency characteristic of the impedance in equation (3) is as shown in Figure 4. That is, the pole ω1 determined by O and RD-CD. ω3
and has a zero point ω2 determined by RD (Cp + Co).

極ω1.ω2はダイオード22の動作電流IDによらず
一定であり、零点ω2はCPを適当に選ぶこと、また、
IDを調整してRDを加えることにより、2つの極ω1
゜ω3の間を自由に変化させうる。従って、そのインピ
ーダンスの周波数特性を第4図に示すように部分的に平
坦な特性とすることができ、しかもその領域を自由に設
定することができる。Cpの調整は集積回路で本回路を
実現するような場合には困難であるが、RDの調整即ち
IDの調整は外部端子から容易に行ないつる。
Extreme ω1. ω2 is constant regardless of the operating current ID of the diode 22, and the zero point ω2 is determined by appropriately selecting CP.
By adjusting ID and adding RD, two poles ω1
It can be freely changed between °ω3. Therefore, the frequency characteristic of the impedance can be made partially flat as shown in FIG. 4, and its region can be freely set. Adjustment of Cp is difficult when this circuit is implemented using an integrated circuit, but adjustment of RD, that is, adjustment of ID, can be easily performed from an external terminal.

第3図+alの回路は、(C)のように震災することが
できる。
The circuit shown in FIG. 3 +al can be affected by an earthquake as shown in (C).

第5図および第6図は本回路の顕著な特長を示すもので
あり、並列に抵抗REを接続したときのイノビーダンス
の周波数特性であり、詔5図は電流IDをパラメータと
したもの、第6図は容量CPをパラメータとしたもので
ある。図において、抵抗Rト二は80Ω、ダイオードの
走行時間τ、は25 pSとしている。第5図は平坦部
のインピーダンスのlさが電流IDで独立に調整しうろ
ことを示しており、IDをかえてもインピーダンスが減
少しはじめる点、即ち極は殆んど変化していない。一方
第6図は自・により独立にインピーダンスから減少しは
じめる点即ち極を調整しうろことを示しておシ、平坦部
のインピーダンスの大きさはCPをかえても変化してい
ない。このようにインピーダンスの極ヲ自由に変化しえ
て、しかも平坦な部分をもつ特性とすることができ、そ
の平坦部のインピーダンスを11L流IDにより任意に
調整しうろことは、特にピーキング増幅器の実現に非常
KuI過である。
Figures 5 and 6 show the remarkable features of this circuit, and show the frequency characteristics of Innovidance when a resistor RE is connected in parallel. The figure shows the capacitance CP as a parameter. In the figure, the resistor R is 80Ω, and the diode transit time τ is 25 pS. FIG. 5 shows that the impedance l of the flat part can be adjusted independently by the current ID, and even if the ID is changed, the point where the impedance starts to decrease, that is, the pole, hardly changes. On the other hand, FIG. 6 shows that the point at which the impedance begins to decrease independently of itself and the poles can be adjusted, and the magnitude of the impedance at the flat portion does not change even if the CP is changed. In this way, the impedance can be freely changed and has a flat part, and the ability to arbitrarily adjust the impedance of the flat part using the 11L ID is especially useful for realizing peaking amplifiers. It's very difficult for KuI.

第7図はピーキング増幅回路の本発明の実施例である。FIG. 7 shows an embodiment of the present invention of a peaking amplifier circuit.

回路構成は入カドランジスタロ、負荷抵抗7 (RLI
) +直列帰還抵抗8(REI)により直列帰還形の増
幅回路が形成されており、3は入力信号端子、4は出力
信号端子、2は低電位電源端子、41はインピーダンス
調整回路である。この増幅回路において、利得は近似的
に次式で表わすことができる。
The circuit configuration is input quadrant transistor, load resistance 7 (RLI
) A series feedback type amplifier circuit is formed by + series feedback resistor 8 (REI), 3 is an input signal terminal, 4 is an output signal terminal, 2 is a low potential power supply terminal, and 41 is an impedance adjustment circuit. In this amplifier circuit, the gain can be approximately expressed by the following equation.

L ””REI/Z Zd第3図のイノピーダンス調整回路のインピーダンス
である。分母のREIと2の並列インピーダンスは先に
説明したように第5図および第6図の周波数特性となる
。従って、利得Gの周波数特性は分子υのインピーダン
スの逆数の形となり、ピーキング量性となる。このl特
性は、第5図、#!6図で説明したように、Cpの設定
によりピーキングを開始する周波数を直流バイアス特性
などと独立に設定でき、しかもピーキング量を電流ID
によって同流バイアス特性、ピーキング開始周波数と独
立に自由に調整可能である。
L "" REI/Z Zd This is the impedance of the inopedance adjustment circuit shown in FIG. 3. As explained above, the denominator REI and the parallel impedance 2 have the frequency characteristics shown in FIGS. 5 and 6. Therefore, the frequency characteristic of the gain G is in the form of a reciprocal of the impedance of the molecule υ, and has a peaking quantity characteristic. This l characteristic is shown in Figure 5, #! As explained in Figure 6, by setting Cp, the frequency at which peaking starts can be set independently of the DC bias characteristics, etc., and the amount of peaking can be set independently of the current ID.
Depending on the cocurrent bias characteristics, the peaking start frequency can be freely adjusted independently.

第8図は本発明のピーキング増幅回路の他の実施例であ
り、■は高電位電諒端イ、2は低電位電源端子、3−1
および3−2は信号人力y;1シ子、4−1および4−
2は信号出力端子、7は負イ’=4r抵抗、8は直列帰
還抵抗、41はインピーダンス調整回路、23はイノビ
ーダンス調整端イである。この増幅回路においても、第
5図の増幅回路と同一の原理でピーキング特性をCpの
選択と外部端子から1昂をat!I御することにより自
由に調整することができる。
FIG. 8 shows another embodiment of the peaking amplifier circuit of the present invention, where ■ is a high potential power supply terminal A, 2 is a low potential power supply terminal, and 3-1 is a low potential power supply terminal.
and 3-2 is signal human power y; 1 shiko, 4-1 and 4-
2 is a signal output terminal, 7 is a negative I'=4r resistor, 8 is a series feedback resistor, 41 is an impedance adjustment circuit, and 23 is an innovidance adjustment terminal A. In this amplifier circuit, the same principle as in the amplifier circuit shown in FIG. 5 is used to select the peaking characteristic of Cp and to obtain one output from the external terminal. It can be freely adjusted by controlling I.

重子説明したように、本発明はコンデンサとダイオード
の微分抵抗を利用し、このダイオードの電流バイアス条
件を制御することによって、インピーダンスを調整、変
化することができる。特にピーキング増幅回路とした場
合はビーキング開始周波数とビーキ/グh土を独立に調
整設定できる0即ち、所望のピーキング開始点からコン
デンサの値を設定し、ピーキング量を外部端子から容易
に調整することができる。従って、4)に集積回路等の
素子値の修正が困難なものでも特性をみながらピーキン
グ量を調整し、安定な増幅器特性を精度よく実現するこ
とができる。これにより、歩留りの向」二、低価格化が
図れ、しかも最大限に広帯域化できるという利点がある
。ピーキング増幅回路のみならず、同調形12+1ち特
定の周lル数特性を有する増幅回路においても、その周
波数特性を外部ψ;Mイから調整することができ、′ピ
ーキング増幅回路と同様の効呆かある。
As Shigeko explained, the present invention utilizes the differential resistance of a capacitor and a diode, and by controlling the current bias conditions of the diode, the impedance can be adjusted and changed. In particular, when using a peaking amplifier circuit, the peaking start frequency and the peak/high frequency can be adjusted and set independently. In other words, the capacitor value can be set from the desired peaking start point, and the amount of peaking can be easily adjusted from an external terminal. I can do it. Therefore, in 4), even if it is difficult to modify element values such as an integrated circuit, the peaking amount can be adjusted while checking the characteristics, and stable amplifier characteristics can be achieved with high precision. This has the advantage of improving yield, lowering costs, and maximizing the bandwidth. Not only the peaking amplifier circuit, but also the tuned 12+1 amplifier circuit, which has a specific frequency characteristic, can have its frequency characteristics adjusted from the external ψ; There is.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のエミッタビーキング増幅回路例を示す回
路図、第2図Ii差動形のエミッタビーギノグ増幅回路
例を示す回路図、第3図は本発明に用いるインピーダン
ス調整回路例を・示す回路図、第4図はインピーダンス
調整回路の動作原理を説明するための図、第5図、第6
図はピーキング調整回路と抵抗のil+2列インピーダ
ンスの周波数特性の一例を示す特性図、第7図、第8図
は本発明のヒ−キング同調整形増幅回路の人施例を)J
<す回路図であるO 1・・・尚′電位1L#端子、  2・・・低電位電蝕
端子、3 、3−1 、3−2・・・イら号入力端了、
  4.4−1.4−2・・・信号出力端子、  6,
10・・・入力トランジスタ、7.15・・・負荷抵抗
、 8,16・・・直列帰還抵抗、9・・・ピーキング
容量、 17・・・定電流回路、21・・・信号入力端
子、22・・・ダイオード、23・・・インピーダンス
調整入力端1.41・・・インピーダンス調整回路。 特許用に「1人  口本電信電話公社 代  理  人   白  水  常  j(fi外1
名 躬3図 J“ (a)              (b)(C) 躬 4  図
Fig. 1 is a circuit diagram showing an example of a conventional emitter beaking amplifier circuit, Fig. 2 is a circuit diagram showing an example of an Ii differential type emitter beaking amplification circuit, and Fig. 3 is an example of an impedance adjustment circuit used in the present invention.・The circuit diagram shown in Figure 4 is a diagram for explaining the operating principle of the impedance adjustment circuit, Figures 5 and 6.
The figure is a characteristic diagram showing an example of the frequency characteristics of the peaking adjustment circuit and the impedance of the il+2 column of resistors, and Figures 7 and 8 show examples of the peaking adjustment type amplifier circuit of the present invention.
<This is a circuit diagram.
4.4-1.4-2...Signal output terminal, 6,
DESCRIPTION OF SYMBOLS 10... Input transistor, 7.15... Load resistance, 8, 16... Series feedback resistance, 9... Peaking capacity, 17... Constant current circuit, 21... Signal input terminal, 22 ...Diode, 23... Impedance adjustment input terminal 1.41... Impedance adjustment circuit. For patent purposes, ``1 representative of Telegraph and Telephone Public Corporation (1 person outside fi.
Figure 3 J” (a) (b) (C) Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)アノード端子とカソード端子を有するダイオード
と、電流値が制御可能で電流値制御端子と電流出力端子
と共通接地端子を有する電流源と、2つの端子を有する
コンデンサとから構成され、ダイオードのアノード端子
が高電位電源に接続され、当該ダイオードのカソード端
子が前記コンデンサの第1の端子と電流源の出力端子と
に接続され、前記電流源の電流値制御端子を調整して前
記コンデンサの第2の端子と接地電位との間のインピー
ダンスを調整しうるインピーダンス調整回路を有するこ
jを特徴とする増幅回路。
(1) Consists of a diode having an anode terminal and a cathode terminal, a current source whose current value is controllable and which has a current value control terminal, a current output terminal, and a common ground terminal, and a capacitor having two terminals. An anode terminal is connected to a high potential power source, a cathode terminal of the diode is connected to a first terminal of the capacitor and an output terminal of a current source, and a current value control terminal of the current source is adjusted to 1. An amplifier circuit comprising an impedance adjustment circuit capable of adjusting impedance between a second terminal and a ground potential.
(2)アノード端子とカソード端子を有するダイオード
と、電流値が制御可能で′電流値制御端子と電流出力端
子と共通接地端子を有するm流源と、2つの端子を有す
るコンデンサとから構成され、ダイオードのカソード端
子が低電位電源に接続され当該ダイオードのアノード端
子が前記コンデンサの第1の端子と電流源の出力端子と
に接続され、前記〜、電流源電流値制御端子を調整して
前記コンデンサの第2の端子と接地′電位との間のイン
ピーダンスを調整しうるインピーダンス調整回路を有す
ることを特徴とする増幅回路。
(2) consisting of a diode having an anode terminal and a cathode terminal, a current source whose current value is controllable and having a current value control terminal, a current output terminal, and a common ground terminal, and a capacitor having two terminals; The cathode terminal of the diode is connected to a low potential power supply, and the anode terminal of the diode is connected to the first terminal of the capacitor and the output terminal of the current source, and the current value control terminal of the current source is adjusted to 1. An amplifier circuit comprising an impedance adjustment circuit capable of adjusting an impedance between a second terminal of the amplifier and a ground potential.
JP13719582A 1982-07-19 1982-08-09 Amplifying circuit Pending JPS5927612A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP13719582A JPS5927612A (en) 1982-08-09 1982-08-09 Amplifying circuit
CA000432581A CA1201775A (en) 1982-07-19 1983-07-18 Monolithic integrated circuit device including ac negative feedback type high frequency amplifier circuit
US06/515,280 US4542350A (en) 1982-07-19 1983-07-19 Monolithic integrated circuit device including AC negative feedback type high frequency amplifier circuit
EP83304191A EP0101201B1 (en) 1982-07-19 1983-07-19 Monolithic integrated circuit device including ac negative feedback type high frequency amplifier circuit
DE8383304191T DE3381390D1 (en) 1982-07-19 1983-07-19 MONOLITHIC INTEGRATED CIRCUIT ARRANGEMENT WITH HIGH-FREQUENCY AMPLIFIER CIRCUIT WITH AC ALTERNATIVE COUPLING.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13719582A JPS5927612A (en) 1982-08-09 1982-08-09 Amplifying circuit

Publications (1)

Publication Number Publication Date
JPS5927612A true JPS5927612A (en) 1984-02-14

Family

ID=15193015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13719582A Pending JPS5927612A (en) 1982-07-19 1982-08-09 Amplifying circuit

Country Status (1)

Country Link
JP (1) JPS5927612A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61210710A (en) * 1985-03-14 1986-09-18 Nec Corp Amplifying circuit for wide band negative feedback
JP2002151985A (en) * 2000-11-13 2002-05-24 Asahi Kasei Microsystems Kk Variable gain amplifier
JP2009290516A (en) * 2008-05-29 2009-12-10 Nippon Telegr & Teleph Corp <Ntt> Differential amplifier circuit
JP2010273058A (en) * 2009-05-21 2010-12-02 Nippon Telegr & Teleph Corp <Ntt> Amplitude limit amplifying circuit
JP2014175763A (en) * 2013-03-07 2014-09-22 Toshiba Corp Variable gain amplification circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS539235U (en) * 1976-07-09 1978-01-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS539235U (en) * 1976-07-09 1978-01-26

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61210710A (en) * 1985-03-14 1986-09-18 Nec Corp Amplifying circuit for wide band negative feedback
JP2002151985A (en) * 2000-11-13 2002-05-24 Asahi Kasei Microsystems Kk Variable gain amplifier
JP2009290516A (en) * 2008-05-29 2009-12-10 Nippon Telegr & Teleph Corp <Ntt> Differential amplifier circuit
JP2010273058A (en) * 2009-05-21 2010-12-02 Nippon Telegr & Teleph Corp <Ntt> Amplitude limit amplifying circuit
JP2014175763A (en) * 2013-03-07 2014-09-22 Toshiba Corp Variable gain amplification circuit

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