JPS5926032B2 - Television video signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a television system in which display data for one screen of television video is stored in a memory, and the display data is read out from the memory in synchronization with television scanning to obtain a television video signal. The present invention relates to a video signal generator.

This type of device divides the television screen into N x M grids created by dividing the television screen into N equal parts in the horizontal direction and M equal parts in the vertical direction. ) is stored in each storage cell of a memory having a number of storage cells equal to the number of grids, and by reading out the stored data from this memory in synchronization with television scanning, a mosaic television image can be created. Generates a television video signal representing .

This type of television video signal generating device is used when processing computer data and displaying the result as a television video. In such cases, the computer performs data processing using the data held in the computer and the data from the terminal device connected to the computer, and the results are displayed in dot data units and as images. It is stored in the memory of the television video signal generator at the output timing of the computer. When new data is added to the computer from the terminal device, data processing is performed using this data, and as a result, only the data that should be changed in the stored display data is written to the memory in units of dot data, and this writing is The previously stored display data is thus changed to the new display data. The display data thus stored in the memory, or modified and stored through subsequent data processing by a computer, is read out in synchronization with television scanning and becomes a television video signal.

When this television video signal is displayed on a television screen, the image contour becomes step-like, which is visually unnatural. In order to reduce the unnaturalness of this contour, it is sufficient to increase the number of equal parts (N and M) of the video screen. However, if the number of equal fractions is increased, the number of grids increases, and the dot data for one stroke increases accordingly, so the memory capacity for storing them increases. Since the output timing from the computer is constant, in other words, the time required for writing dot data units from the computer to the memory of the television video signal generator is constant, so as the dot zeta increases, the memory capacity increases. Along with the increase, there was a drawback that memory writing time took a correspondingly longer time. Therefore, an object of the present invention is to increase the number of equal divisions of an output television image in the horizontal and vertical directions and to increase the memory capacity in order to eliminate unnatural image contours. It is an object of the present invention to provide a television video signal generating device in which display data writing time does not increase accordingly.

According to the present invention, there is provided a memory for storing display data for one screen of a television image, a write control means for controlling writing of the display data into the memory, and a television scan for the display data from the memory. a read control means for reading data in synchronization with the first means, wherein the write control means writes each of the dot data corresponding to each storage cell of the memory on a one-to-one basis into each of the storage cells; A television video signal generating device is obtained which has second means for writing each of the dot data into a plurality of the storage cells, and means for switching between the first and second means.

In the television video signal generating device according to the present invention, there is a mode in which dot data of display data to be written is written one-to-one into memory cells of the memory corresponding to the dot data when writing display data from the computer to the memory at the output timing of the computer; The mode of writing to individual memory cells (one vs. multiple cells) can be switched.
Display data to be written (output data from the computer)
Not only can the increase in memory writing time be suppressed by switching modes depending on the situation, but also the time can be significantly shortened depending on the content of the display data to be written.

The objects, configurations, and effects of the present invention described above will become clearer from the following description with reference to the drawings showing embodiments of the present invention.

Referring to FIG. 1, the embodiment of the present invention shown in this figure is an example applied to a device that processes four dot data (one group) with one command from a computer.

This embodiment includes a television video signal generator 10, a data input device 11, and a computer 12 according to the present invention.
and a monitor 13. Data input device 11
The data from the computer 12 and the data held in the computer 12 are processed by the computer 12. The computer 12 displays display data D that represents data to be displayed or data to be changed in units of dot data, and indicates whether each dot data of the display data D is to be written into the storage cells of the memory one-to-one or in a -pair-to-multiple format. Mode data M and address information A of dot data groups are supplied to the television video signal generator 10 in units of 4 dot data (one group) in one command. The television video signal generator 10 includes a memory 15 that records display data for one screen of television video, a write control circuit 16 that controls writing of display data D to the memory 15, and a write control circuit 16 that controls writing of display data D to the memory 15. It has a read control circuit 17 that reads stored data in synchronization with scanning, and a write/read switch 18 that switches between writing and reading operations of the memory 15.

As shown in FIG. 2, the write control circuit 16 is a first gate circuit for supplying four dot data DO-D3 that are simultaneously supplied to each storage cell #o to #n1 of the memory 15 on a one-to-one basis. Group 21 (21-0, 21-1, 21-2, 2
1-3) and four dot data D. - D3 to memory 1
A second gate circuit group 22 (22-0, 22-1, . . .
22-7), a gate control circuit 23 that generates a signal to select one of the first and second circuit groups 21 and 22 according to the mode data M, and a gate control circuit 23 that receives the address information A and controls the write address. and a gate circuit group 25 for supplying dot data from the first circuit group 21 or the second circuit group 22 to each storage cell of the memory 15 under the control of the address control circuit 24. It has The data supplied from the computer 12 is, for example, graphical data as shown in FIG.
In the case of data between points a and b, and between points c and h, mode data M selects the first circuit group 21 and writes dot data into the memory cells one-on-one, and between points b and c. c.
and between points h and j, select the second circuit group 22 and write dot data to the memory cells in one-to-many format (in the case of this embodiment, one dot data to two memory cells). It is.

In addition, when characters and figures are mixed, the first circuit group 21 is selected for the text part and the dot data is written one-to-one into the memory cells, and the second circuit group 22 is selected for the figure part.
The computer supplies data for selecting the dot data and writing the dot data into the memory cells in a one-to-many manner. Among the data from the computer 12, four dot data D
(DO-D3) is supplied to the corresponding gate circuits of the first and second gate circuit groups 21 and 22, mode data M is supplied to the gate control circuit 23, and address information A is supplied to the address control circuit 24.

For example, when the mode data M is "1", the gate control circuit 23 selects the first gate circuit group 21.Thereby, the dot data D.
It is supplied to each of the data lines 25-o to 25-3 via 21-3. When the mode data M is "0", the gate leg circuit 23 selects the second gate circuit group 22. This results in dot data D. is the gate circuit 22-o
and 22-1 via data lines 26-o and 26
-1, dot data D1 passes through gate circuits 22-2 and 22-3 to data lines 26-2 and 22-3, and dot data D2 passes through gate circuits 22-4 and 22-3.
5 to data lines 26-4 and 26-5, and further the dot data D3 is sent to gate circuits 22-6 and 22-5.
7 to data lines 26-6 and 26-7, respectively. On the other hand, the address information A supplied from the computer 12 to the address control circuit 24 is associated with the mode data M, and when the mode data M is "1", the mode data M can simultaneously control the addresses of four memory cells. In the case of "0", addresses of 4m memory cells (m is an integer of 2 or more, in this embodiment, M2) are simultaneously represented.

That is, when the mode data M is [1], the address data line 27 (27-0, 27-1, . . .
・27-(enemy-1)), when mode data M is "O", address data line 28(28-0, 28-1,
A signal for selecting the gate circuit group 25 is sequentially supplied to . Mode data M
When is "1", dot data D is supplied to data lines 25-o to 25-3. ~D3 is written into the corresponding storage cell in response to an address signal supplied to one of the address data lines 27. That is, when an address signal is supplied to address data line 27-o, dot data D is supplied to data lines 25-o to 25-3. -D3 is written in each of the memory cells #o to #3 of the memory 15, and when the address signal is supplied to the address data line 27-1, the dot data D at that point is written.
. -D3 is written into storage cells #4 to #7 of the memory 15, respectively. Similarly, when an address signal is supplied to one of the address data lines 27, the dot data D at that time. -D3 are simultaneously written one-to-one to the memory cells corresponding to the address data lines supplied with the address signal. Dot data D is supplied to data lines 26-o to 26-7 when mode data M is 1-0.

~D3 are respectively written into two corresponding storage cells in response to an address signal supplied to one of the address data lines 28. That is, when an address signal is supplied to the address data line 28-o, the dot data D. is written in memory cells #0 and #1, dot data D1 is written in memory cells #2 and #3, dot data D2 is written in memory cells #4 and #5, and dot data D3 is written in memory cells #6 and #7, respectively. It will be done. When an address signal is supplied to the address data line 28-1, the dot data D at that time. ~D3 is memory cell #8
~Written in #15. In the same manner, when an address signal is supplied to one of the address data lines 28, the dot data D at that time is generated. -D3 is written to two memory cells for one dot data. In this way, depending on the mode data M, the four dot data supplied simultaneously are written one-to-one into four memory cells, or written one-to-two into eight memory cells.

Since the cycle time of the data supplied from the computer 12 is constant, if dot data is written into the memory cells in a one-to-two ratio, the writing time per unit length on the screen is halved compared to the case of one-to-one. can. Therefore, in the case of the figure in Fig. 3, the writing time per unit length between points b and c and between points h and j is equal to the writing time per unit length between points a and b and between points c and h. This is half the write time, and if the number of memory cells into which one dot data is written is increased, the write time per unit length can be shortened accordingly. Data is read from the memory 15 in which display data has been written in this manner under the control of the read control circuit 17 in synchronization with television scanning, and a television video signal is obtained at the output terminal 14.

By supplying this television video signal to the monitor 13, the data stored in the memory 15 can be monitored. Next, new data is supplied from the data input device 11 to the computer 12 for processing, and if the computer 12 determines that a part of the image on the display screen should be changed, the computer 12 inputs the dot data of the part that needs to be changed. D and mode data M are supplied to write control circuit 16 along with address information A.

The write control circuit 16 writes each piece of dot data D in a one-to-one or one-to-multiple manner in accordance with the mode data M to the memory cell corresponding to the address information A. As a result, part of the stored video is changed in accordance with data from the computer 12. Although the embodiment described above is an apparatus that processes 4 dot data with one command from a computer, it is possible to process 4 dot data with a different number of dot data/commands than that of this embodiment.

Furthermore, although the case where the memory array is sequentially arranged in the horizontal direction for writing has been described, it is also possible to sequentially arrange and write in the vertical direction, or to arrange irregularly in the horizontal and vertical directions and write simultaneously. Since these modifications will be obvious to those skilled in the art from the description of the embodiments, their description will be omitted. As described above in detail, in the television video signal generator according to the present invention, when storing each dot data in the memory, there is a first mode in which each dot data is written in the storage cells of the memory one-to-one, and a second mode in which it is written one-to-many in a one-to-many manner. For example, the first mode can be selected for data that changes minutely in the horizontal direction, and the second mode can be selected for areas that do not change. As a result, even if dot data and memory storage cells (memory capacity) increase by increasing the number of equal parts of the screen, it is possible to suppress an increase in the time required to write data into the memory.

[Brief explanation of drawings]

Fig. 1 is a block diagram of one embodiment of the present invention, and Fig. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a detailed block diagram of a portion of the embodiment shown in the figure, and is a diagram for explaining the operation of the present invention.

Claims (1)

[Claims] 1 a memory for storing display data for one screen of television video; a write control means for controlling writing of the display data into the memory using external control data and address data; In the television video signal generating device, the writing control means includes a plurality of first gate means for receiving the display data, and a readout control means for reading data in synchronization with the external control data. a gate control means for generating a gate signal for controlling the gate means; and a plurality of second gate means for receiving the output of the first gate means and the address data; A television video signal generating device characterized in that an output is connected to each storage cell of the memory.