JPS5925244A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5925244A JPS5925244A JP57133711A JP13371182A JPS5925244A JP S5925244 A JPS5925244 A JP S5925244A JP 57133711 A JP57133711 A JP 57133711A JP 13371182 A JP13371182 A JP 13371182A JP S5925244 A JPS5925244 A JP S5925244A
- Authority
- JP
- Japan
- Prior art keywords
- region
- diode
- substrate
- junction
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000006378 damage Effects 0.000 claims description 2
- 238000009966 trimming Methods 0.000 abstract description 8
- 238000002161 passivation Methods 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- NFLLKCVHYJRNRH-UHFFFAOYSA-N 8-chloro-1,3-dimethyl-7H-purine-2,6-dione 2-(diphenylmethyl)oxy-N,N-dimethylethanamine Chemical group O=C1N(C)C(=O)N(C)C2=C1NC(Cl)=N2.C=1C=CC=CC=1C(OCCN(C)C)C1=CC=CC=C1 NFLLKCVHYJRNRH-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000010009 beating Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置に関するものである。[Detailed description of the invention] The present invention relates to a semiconductor device.
演羽増幅器においては、入力段に接続された抵抗を調整
してゲインをトリミングすることがある。In a performance amplifier, the gain may be trimmed by adjusting a resistor connected to the input stage.
本発明者は、そうしたゲイントリミングをはじめとする
種りの回路投首１にとって極めて有用な構造を見出１〜
、本発明に到達したものである。The present inventor has discovered a structure 1 to 1 which is extremely useful for various types of circuits 1 including such gain trimming.
, this invention has been achieved.
即ち、本発明は、半導体基体に形成されたＰＮ接合がレ
ーザー光によって選択的に熱破壊され、この選択的な短
絡構造によって例えば上述したトリミング等が行なわれ
るようになしたことを特徴としている。こうしたレーザ
ー照射による短絡構造は、従来の電流破壊方式における
如き配線＋′電極パッド、プローバ等が全く不要であり
、しかもファイナルパッシベーション膜形成後又ハハソ
ケージ封止後のレーザー照射が可能であって製品の完成
に要する時間を大幅に短縮することができろ。That is, the present invention is characterized in that a PN junction formed on a semiconductor substrate is selectively thermally destroyed by laser light, and this selective short-circuit structure is used to perform, for example, the above-mentioned trimming. This type of short-circuit structure by laser irradiation does not require wiring + electrode pads, probers, etc. as in the conventional current breakdown method, and furthermore, laser irradiation can be performed after the final passivation film is formed or after the cage is sealed. The time required for completion can be significantly reduced.
更ニ、レーザー光のスポット径は数７７ ′ｎ１と微小
に絞れることから、熱破壊領域を小さくし、微細加工を
選択的に行なうことができる。Furthermore, since the spot diameter of the laser beam can be narrowed down to a microscopic number of several 77'n1, the thermal destruction area can be made small and fine processing can be selectively performed.
以下、本発明の実施例を図面について詳イ［［１に説明
する。Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は、本発明が適用されるゲイントリミング回路の
等価回路を示すものであって、演算増幅器の入力段には
入力抵抗Ｒ、ｎ、微調整用の各抵抗ｒ、スイッチ用の各
ＭＩＳＦＥＴＱおよびＱ′が接続され、またその出力段
には出力抵抗ｒ（ｆが接続されている。そして各Ｆ Ｅ
Ｔ Ｑ、のゲートには、ポリＳ１抵抗Ｆ（及びＰＮ接
合ダイオードＤが各可、源との間に接続されている。FIG. 1 shows an equivalent circuit of a gain trimming circuit to which the present invention is applied, in which the input stage of the operational amplifier includes input resistors R, n, resistors r for fine adjustment, and MISFETs Q for switches. and Q' are connected, and an output resistor r(f is connected to its output stage. And each F E
A poly S1 resistor F (and a PN junction diode D is connected between the gate of TQ and the source of each transistor).
このゲイントリミング回路におい−〔は、まずセンター
のＦ Ｅ Ｔ Ｑ、’を介してゲインを測定後に、各Ｆ
Ｅ Ｔ Ｑのいずれかをオンさせ、抵抗ｒ分によって
入力抵抗をｙｈ ｆｐｌａ ｔ、てゲインをトリミング
することができる。このために、本実施例によれば、」
二記スイッチ用１” Ｅ Ｔ Ｑの部分が第２図の如く
に構成され、ダイオードＤがレーザー照射によって選択
的に破壊されろようにしている。In this gain trimming circuit, after first measuring the gain through the center FETQ,',
The gain can be trimmed by turning on either E T Q and adjusting the input resistance by the resistor r. To this end, according to this embodiment, "
The 1" ET Q section for the second switch is constructed as shown in FIG. 2, so that the diode D can be selectively destroyed by laser irradiation.
即ち、Ｎ−型シリコン基板１の一生面に形成されたＰ型
ウェル２にＮ１型ソース領域３及びドレイン領域４、ゲ
ート酸化膜５、ポリシリコンゲート′ｒｒｉ極６からな
るＦ Ｅ Ｔ Ｑが設けられ、またフィールドＳｉＱ、
膜７で［７１まれだ基板領域には上記のダイオードＤを
構成−［ろＰ＋型半導体領域８が形成され、更にフィー
ルドＳｉＱ、膜７−にに上記のポリシリコン抵抗ｉｔ
（こＡしはゲート軍、極６と同時に形成されてよい）が
設けられている。なお、図中の９はリンガラス膜、１０
．１１．１２．１３は各アルミニウム軍、極、１４はフ
ァイナルパソシベーシ１ン膜である。That is, a FETQ consisting of an N1 type source region 3, a drain region 4, a gate oxide film 5, and a polysilicon gate'rri electrode 6 is provided in a P type well 2 formed on the whole surface of an N- type silicon substrate 1. and field SiQ,
In the film 7, a P+ type semiconductor region 8 is formed in which the diode D described above is formed, and the polysilicon resistor it is formed in the field SiQ and the film 7-.
(This is a gate army, which may be formed at the same time as pole 6). In addition, 9 in the figure is a phosphorus glass film, 10
．． 11, 12, and 13 are each aluminum layer and pole, and 14 is a final passivation film.
このようにファイナルパソシベ〜ジョン（更にハパッケ
ージ制止）を施した後に、第３図の如くに所定のダイオ
ードＤ上からレーザー光１５を照射するうこのレーザー
光は例えばＮ、レーザーで発生せしめられ、波長５１０
０Ａ、対物レンズ面前のエネルギー６０ｍＶ、パルス幅
ＩＱｎｓ、繰返し周波数１〜５０）１ｚ、スポット径３
μｍφであってよい。このレーザー照射によって、各表
面膜を通してレーザー光１５が基板１側へ到達し、ダイ
オードＤのＰＮ接合が熱破壊されろ。この結果、ダイオ
ードＤのＰ 型領域８と基板１とが短絡せしめられ、第
４図に等測的に示したダイオードＤが単なる抵抗Ｉｌ′
に変化し、Ｐ＋型領域８と基板ｌとの間にオーミック接
合が生じろことになる。このため、レーザー照射前には
ＦＥＴＱのノード（ゲート）には−５■が印加されてＦ
Ｅ Ｔ Ｑがオフとな）っているか、上記のレーザー服
射によるダイオードＤの破壊後は基板電圧（＋５ Ｖ
）が与えられることになり、ＦＥＴＱがオンとなる。従
って、この選択重圧導通せしめられたＦ Ｅ Ｔ Ｑを
弁じて枡抗ｒ分、具体的に目−ｎｒ（ｎはＲ、ｏからみ
た抵抗ｒの数少が入力抵抗として入るから、この増幅器
のゲインを所望の値にトリミング１″ることかできる。After performing the final passivation (further package restraint) in this way, the laser beam 15 is emitted from above a predetermined diode D, as shown in FIG. , wavelength 510
0A, energy in front of the objective lens 60mV, pulse width IQns, repetition frequency 1 to 50) 1z, spot diameter 3
It may be μmφ. By this laser irradiation, the laser beam 15 reaches the substrate 1 side through each surface film, and the PN junction of the diode D is thermally destroyed. As a result, the P-type region 8 of the diode D and the substrate 1 are short-circuited, and the diode D shown isometrically in FIG. 4 becomes a mere resistor Il'.
This results in an ohmic junction between the P+ type region 8 and the substrate l. Therefore, -5■ is applied to the node (gate) of FETQ before laser irradiation, and FET
The substrate voltage (+5 V
) is given, and FETQ is turned on. Therefore, by controlling this selective heavy pressure conduction FETQ, the square resistance r is calculated, specifically -nr (n is R, and since a fraction of the resistance r seen from o enters as the input resistance, the amplifier's The gain can be trimmed 1'' to the desired value.
上記したことから明らかなよりに、このゲイントリミン
グのだめのレーザー照射は！棟品の半完成又は守成状態
で行なえるから、いわゆるＴΔ′ｒ（Ｔｕｒｎ Ａｒｏ
ｕｎｄ Ｔｉｍｅ ）を大幅に短縮できる。It is clear from the above that this laser irradiation is useless for gain trimming! Since it can be carried out with the ridge piece in a semi-completed or guarded state, it is possible to perform the so-called TΔ'r (Turn Aro
and time) can be significantly shortened.
従来の電流破壊方式では、プロピングチスト後に熱処理
下４？が入り、特性の変動が生じ易いが、本笑施例では
そのようなことはなく、かつ配線、バッド及びグローバ
が不要となり、歩留及び作業性も非′帛に向上すること
になる。しかも、レーザー１［＋４射によることから、
レーザー光のエネルギーが樋方向に拡がり価く、小スポ
ット径に絞れ、ＰＮ接合を選択的に破壊−「ろことがで
きイ）。In the conventional current breakdown method, heat treatment is performed after propagation test. However, this embodiment does not cause such a problem, and also eliminates the need for wiring, pads, and glovers, and significantly improves yield and workability. Moreover, since it is based on laser 1 [+4 shots,
The energy of the laser beam spreads in the direction of the gutter and can be narrowed down to a small spot diameter, selectively destroying the PN junction.
第６図及び第７ジｊは、別の実施例を示すものである。6 and 7 show another embodiment.
例えば、Ｐ″ｉ（リソース領域２３及びドレイン領１１
１４２４ 、 ゲートｔｒｙ析２６からなるＰチャネ
ルＭＩＳ Ｆ ＥＴ Ｑにおいて、アルミニウムの市、
源配紳２０をドレイン領域２４に接続しようとした場合
、ドレイン領域２４上に配線２０炒着用のコンタクトポ
ールを形成し忘れることがある。この場合圧はドレイン
領域２４へは所定の宵源朗、圧が供給されないことにな
り、不都合である。For example, P″i (resource region 23 and drain region 11
1424, P-channel MISFET Q consisting of gate try analysis 26, aluminum city,
When attempting to connect the source wiring 20 to the drain region 24, it may be forgotten to form a contact pole for frying the wiring 20 on the drain region 24. In this case, a predetermined pressure is not supplied to the drain region 24, which is disadvantageous.
そこで、第７図のよう罠、上述したと同様に、レーザー
光１５を照射してドレイン領域２４と基板１との間のＰ
Ｎ接合を熱的に破壊することによって、両者間を短絡さ
せ、ドレイン領域２４に基板電圧（アルミニウム配線２
０によろ■、源叩圧と同じ可、圧）を供給することがで
きる。Therefore, as shown in FIG.
By thermally destroying the N junction, a short circuit is created between the two, and the substrate voltage (aluminum wiring 2
It is possible to supply the same pressure as the original beating pressure).
なお、上述した実施例は他のデバイスヌは回路、例えば
Ａ／Ｉ）、Ｄ／Ａ変換器等の若量ヌは抵抗トリミング、
ＦＲＯＭの書込み、ＲＡＭの不良ビットの救済、不良解
析９周波数又は方式選択等の機能選択、マスタースライ
ス方式に応用可能である、上述のトリミング以外にも、
電源ラインの省略。In addition, in the above-mentioned embodiment, other devices are circuits (for example, A/I), D/A converters, etc. are resistor trimming,
In addition to the above-mentioned trimming, which can be applied to FROM writing, repair of defective bits in RAM, selection of functions such as failure analysis 9 frequency or method selection, and master slice method,
Omission of power line.
半完成品での配線変更等を実駅できろ。また、熱破壊さ
れるべきＰＮ接合は、上述のＰＮダイオ−トに限らず、
Ｐ型基板に形成したＮ型領域によるダイオードもイ史用
＋５７能である。Please make wiring changes to the semi-finished product at the actual station. Furthermore, the PN junction to be thermally destroyed is not limited to the above-mentioned PN diode.
A diode with an N-type region formed on a P-type substrate also has a +57 function.
図面のｆハ゛ｉｊｉ′！な説すｊ
第１同はイ・発明の実施例によろ演ｎ増幅器の等価回路
図、
第２図はスイッチ用のＭ Ｉ Ｓ ＦＥ’Ｉ’部分の断
面図、
卯、３図はレージ“−照射時のダイメート部分の断面図
、
第４図はレーザー照射前のダイオード、第５図はレーザ
ー照射後の同ダイ牙−ド部分、第６図は別の例によろＭ
Ｉ Ｓ Ｆ Ｅ Ｔの平面図、第７図はレーザー照射
時の第７図のＸ−Ｘ線一部断面図である。The drawing's f-hiji'! Figure 1 is an equivalent circuit diagram of an amplifier according to an embodiment of the invention, Figure 2 is a cross-sectional view of the MISFE'I' part for the switch, Figure 3 is a circuit diagram of the amplifier. - A cross-sectional view of the dimate part during irradiation, Figure 4 shows the diode before laser irradiation, Figure 5 shows the same diode part after laser irradiation, and Figure 6 shows another example.
FIG. 7 is a plan view of ISFET, and is a partial sectional view taken along the line X--X in FIG. 7 during laser irradiation.
９−リンガラス膜、１４・フアイナルパツシベーシヨン
膜、１５・・レーザー光、２０・・γδ１源配線、Ｑ、
Ｑ’−〜ｌ Ｉ Ｓ ＦＥ Ｔ、ＩＪ−・ヅイオード
、ｒ −）リミング用の徂抗、１（・・ボ’ＪＳｉｔｌ
ｌｉ抗。9-Phosphorus glass film, 14. Final passivation film, 15. Laser light, 20. γδ1 source wiring, Q.
Q'-~l I S FET, IJ-・diode, r-) Rimming resistance, 1 (...Bo'JSitl
li anti.
Claims (1)
れた第２導電型の半導体領域とによってＰＮ接合が形成
され、このＰＮ接合が前記半導体基体上からのレーザー
光の照射によって選択的に熱破壊され、この熱破壊で前
記半導体領域と前記半導体基体とが短絡せしめられてい
シ）ことを特徴とする半導体装置。1. A PN junction is formed by a semiconductor substrate of a first conductivity type and a semiconductor region of a second conductivity type formed on this semiconductor substrate, and this PN junction is selectively irradiated with laser light from above the semiconductor substrate. 1. A semiconductor device characterized in that the semiconductor region is thermally destroyed, and the semiconductor region and the semiconductor substrate are short-circuited by the thermal destruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57133711A JPS5925244A (en) | 1982-08-02 | 1982-08-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57133711A JPS5925244A (en) | 1982-08-02 | 1982-08-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5925244A true JPS5925244A (en) | 1984-02-09 |
Family
ID=15111103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57133711A Pending JPS5925244A (en) | 1982-08-02 | 1982-08-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5925244A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63145514A (en) * | 1986-12-08 | 1988-06-17 | Toshiba Corp | Stabilizing circuit for base current of transistor |
| US5013678A (en) * | 1986-11-18 | 1991-05-07 | Siemens Aktiengesellschaft | Method of making an integrated circuit comprising load resistors arranged on the field oxide zones which separate the active transistor zones |
| US5075250A (en) * | 1991-01-02 | 1991-12-24 | Xerox Corporation | Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead |
-
1982
- 1982-08-02 JP JP57133711A patent/JPS5925244A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5013678A (en) * | 1986-11-18 | 1991-05-07 | Siemens Aktiengesellschaft | Method of making an integrated circuit comprising load resistors arranged on the field oxide zones which separate the active transistor zones |
| JPS63145514A (en) * | 1986-12-08 | 1988-06-17 | Toshiba Corp | Stabilizing circuit for base current of transistor |
| US5075250A (en) * | 1991-01-02 | 1991-12-24 | Xerox Corporation | Method of fabricating a monolithic integrated circuit chip for a thermal ink jet printhead |
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