JPS5925219A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the disconnection of Al wires as well as to form the wiring electrode which can be highly integrated for the titled semiconductor device by a method wherein a flat surface is formed in advance by filling up the first Al wiring film in the concavity of an electrode window. CONSTITUTION:An insulating layer 32 is formed on a semiconductor substrate 31, and a polycrystalline silicon layer 23 is formed on said insulating layer 32. Then, a desired resist film mask 34 is formed on the polycrystalline silicon layer 33, an isotropic etching is performed on said polycrystalline silicon layer 33, and then an anisotropic etching is performed on the insulating layer 32. On the whole surface of the semiconductor substrate 31, a wiring metal film 35 is vapor-deposited, said metal film 35 is lifted off and removed by removing the resist film 34, and then the polycrystalline silicon layer 33 located on the whole surface is removed. Subsequently, works are proceeded in accordance with the ordinary procedures.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor (f) IC device (U), and more particularly to a method for forming wiring electrodes.

0 power Technology behind the scenes jj (i:s, f, "14h'h") As the density and speed of semiconductor devices are rapidly increasing, technologies for forming electrodes with fine pattern multilayer wiring structures are being integrated. It has become an important technology that influences the improvement of efficiency and performance.

(C) Prior Art and Problems 256 Memory - As the degree of integration of 1M memory and LSI increases, electrode window dimensions are becoming smaller. In addition, there is a trend toward using plastic packages to reduce costs, and insulation surface retention films (circle 10sllho 5lli
It became necessary to lower the phosphorus concentration of the metal wiring film (At) and the semiconductor substrate, and even after heat treatment for ohmic contact between the metal wiring film (At) and the semiconductor substrate, the electrode windows tend to have sharp steps and vertical sides. The risk of At disconnection is increasing. 1 The following is explained with reference to the drawings:
Figures 1 and 2 show the semiconductor device! II! 1A is a cross-sectional view of a main part for explaining a conventional method of forming one layer of wiring film in a manufacturing method. First, as shown in FIG. 1(a), insulation M (P, S, G, ) 12 is deposited and the required electroplating (
[Window] 3 is selectively formed. Next, as shown in FIG. 1 (1), a metal wiring film 1.1 such as KAt is deposited on the entire surface of the two-dimensional substrate 11, and the desired pattern is formed using the usual photo-etching method. 1, and then a heat treatment is performed to form an ohmic contact between the semiconductor substrate 11 and the gold scraps 1, 1, 1, and 1, as shown in FIG.

However, with the increase in the degree of integration, electricity (viewing window 1:3
As the dimension t tends to become smaller and finer, there is a risk of At disconnection occurring at the window edge portion 121, and in a multilayer wiring structure in which one more layer of At wiring is provided, the unevenness of the 1st layer will become stronger. There is a danger of connecting to the lfl'1' wire (W) Electric power (11), especially when using a plastic package, it is necessary to reduce the phosphorus concentration of the PSG insulating layer 12.
The window edge 121 is hardly melted even by heat treatment, and the step tends to stand vertically, increasing the risk of At wire breakage. Figure 2 shows how to solve the problem of ``Una!''. 11.V method can also be considered - C color. That is, the secret 2 is applied to the insulating layer 22 deposited on the surface of the semiconductor substrate 21.
3, in order to prevent the thin lines of the At wiring from forming on the side surfaces of the windows 2 and 3, 1k (13~Window\J method I is described above) 111:
The problem arises that it becomes thicker than the original modulus t, which is disadvantageous when increasing the degree of integration.

(d) Purpose of the Invention The first object of the present invention is to fill the four parts of the electrode window with a first At wiring film to form a flat surface, and then form a second At wiring film to prevent At disconnection. It is an object of the present invention to provide a method for forming the wiring 11 in a pole shape that can be prevented and highly integrated.

(e) Structure of the Invention The method for manufacturing and using a semiconductor device of the present invention is characterized by the steps of forming an insulating layer on a semiconductor substrate, further forming a polycrystalline silicon layer on the insulating layer, and Forming a desired resist film 340 on the silicon layer, isotropically etching the polycrystalline silicon layer, then anisotropically etching the insulating layer, and depositing a wiring metal film on the entire surface of the semiconductor substrate-1x. 1. Lift-on and remove the metal film by removing the n'I RQ resist film, and further removing the entire surface of the polycrystalline silicon layer.

Embodiment of the Invention Hereinafter, an embodiment of the present invention will be explained in detail with reference to the drawings. Fig. J 1/(I11 is formed, and then about 1,000 polycrystalline silicon layers are deposited on the insulating layer 32, and a desired resist film 34 to 734 is formed on the polycrystalline silicon 12 layer at a ratio of 3:1. Next, as shown in FIG. 2(b), the resist film 34 is masked and etched using a cylindrical plasma etching device F/.
, etc., the polycrystalline silicon layer 3;
Perform IL editor. At this time, one resin film 3-r (in the yellow direction) was
It is necessary to form a

Next, as shown in the same figure (c), C was further applied to a parallel plate type ion etching apparatus using the 3:3 resist film as a mask.
Anisotropic etching is performed using a reactive gas such as F, etc. to vertically etch the insulating film 32 to form a window 321 with the same dimensions as the required pattern.
As shown in d), high vacuum (
](]-"l'orr) to evaporate a wiring gold film such as normuminium (At). −Ni-Ni each]
At wiring film: +5r: 35' is formed, but the first At wiring film 35 of i'+iJ and the first A4 wiring film of resist film 340;) 5' are not connected by the undercut 3.11. do not have. Next, the At wiring film 35' is removed by the lift-off method as shown in FIG. By removing the polycrystalline silicon layer 33 using a gas such as CF using a type plasma etching device, the first A, f'iF! line film 35 having a flat surface is completed. Of course, the insulating layer 32 is hardly removed by the CI'' Blaze 7 etching due to its selectivity.

The subsequent steps may be carried out according to conventional methods. For example, as shown in FIG.
A two-layer wiring is completed by vapor-depositing t wiring (Ji! jls! 36). Also, although not shown, the method using the above embodiment may be repeated to form a multi-layer wiring of three or more layers. Of course, it is also possible.

2-According to the embodiment, the electrode window 321 can be easily removed by the lift-off method by providing the undercarriage 131 part.
The concave f411 is filled with the first At wiring film 35, and the first At wiring 1 (
Can form a tail. (Me〔〇〇This 1st At
r:n,! , tri<film>, the second At pattern (i!if lIl^) is unlikely to cause disconnection or pattern disturbance.

The present invention is not limited to the above-mentioned examples, but departs from the spirit thereof and is not limited to the above-mentioned examples. Modifications can be implemented. .

(g) Effects of the Invention - 1 - According to the present invention as explained, it is possible to easily fill one part of the first At wiring in the recess C of the electrode window and form a flat surface on the L1 semiconductor substrate. At1tJi
Prevent wire +, f-L N and high concentration fJ” (degree wiring +1
Confidence has improved as Il+ can be formed with high precision.
The second has a big effect.

4 Energy-saving explanation of if+i No. 11:<l, CiS Figure 2 shows the main part of the conventional method (Fig. 1; Noj+i+i diagram.

In the figure, °C131 is a semi-quadruple board, 32 is an insulating layer,
331 Yota 1 paleo-crystalline 1 layer, 3.1 is resist type!
, , 15, 35' is the first A/= arrangement line membrane, 3G is the second Atl''II! line membrane, :12] is the electrode window, 3
31 is Anotaka Soto) < 1 (.

Claims (1)

[Claims] Semiconductor substrate-1- (forming an insulating layer, and further forming the insulating layer)
A process of forming a polycrystalline silicon layer on -, forming a desired resist film mask on the polycrystalline silicon layer, isotropically etching the polycrystalline silicon layer, and then forming the insulation jτ1 of 01J. Anisotropic etching step: - Depositing a wiring metal film over the entire surface of the semiconductor substrate, removing the resist film by lifting-on the metal film, and then removing the polycrystalline silicon layer over the entire surface.゛I', conductor device i77 characterized in that it includes a removal step
manufacturing method.