JPS592477A - System for testing digital signal generator - Google Patents

System for testing digital signal generator

Info

Publication number
JPS592477A
JPS592477A JP10998682A JP10998682A JPS592477A JP S592477 A JPS592477 A JP S592477A JP 10998682 A JP10998682 A JP 10998682A JP 10998682 A JP10998682 A JP 10998682A JP S592477 A JPS592477 A JP S592477A
Authority
JP
Japan
Prior art keywords
signal
line
multiplex
digital signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10998682A
Other languages
Japanese (ja)
Inventor
Shigeki Shimazaki
茂樹 島崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10998682A priority Critical patent/JPS592477A/en
Publication of JPS592477A publication Critical patent/JPS592477A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/22Arrangements for supervision, monitoring or testing
    • H04M3/24Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H04M3/244Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

PURPOSE:To measure simply and accurately an output of a signal generator, by measuring an output of a multiplex separation gate passing a specific time slot of a time division exchange output on a multiplex line at a digital signal test device. CONSTITUTION:Outputs of an audible signal generator 1 and a multi-frequency signal generator 2 generating respectively a digital signal are transmitted to an optional time slot TS on the 1st multiplex line 6 with a multiplexer 3. The signal on the line 6 is connected to the 2nd multiplex line 8 via a time division switch 7 to be corresponded to an optional TS and a signal of each TS on the line 8 is separted and extracted to an optional TS with an FF10A of a multiplex separating device 9. The device 9 is provided with a multiplex separating control circuit 11, an output of the circuit 11 according to an external command controls a multiplex separating FF10B to pass a specific TS on the line 8. An output of the FF10B is inputted to a digital signal test circuit 13 and a decoder 14, the circuit 13 tests the frequency an level of the digital signal for displaying it and the audible tone of the output of the decoder 14 is confirmed at a receiver 15.

Description

【発明の詳細な説明】 本発明は、時分割交換機に使用される可聴信号。[Detailed description of the invention] The invention relates to an audio signal used in a time division switch.

多周波信号等をデジタル値として出力するデジタル信号
発生器の出力信号の正常性を試験するデジタル信号発生
器試験方式に関する。
The present invention relates to a digital signal generator test method for testing the normality of an output signal of a digital signal generator that outputs a multi-frequency signal or the like as a digital value.

従来、この種デジタル信号発生器の正常性を試験するた
めには、通話路試験装置を交換機の加入者回路に接続し
て、該通話路試験装置から擬似的に呼を発生することに
より、交換機に一般的な交換動作を行なわせ、その過程
で発生する各種可聴信号、多周波信号等を前記通話路試
験装置で受信して試験する方法が採られている。従って
、試験のための操作に時間がかかり、また、アナログ信
号に復号された状態で受信されるため、途中の加入者回
路、符号復号回路等で減衰、変形等された信号をチェッ
クすることしかできない。すなわち、試験に時間を要し
、しかも正確な信号発生器の出力の測定ができないとい
う欠点がある。
Conventionally, in order to test the normality of this type of digital signal generator, a communication path test device was connected to the subscriber circuit of the exchange and a pseudo call was generated from the communication path test device. A method is adopted in which the communication path testing device receives and tests various audible signals, multi-frequency signals, etc. generated in the process by performing a general switching operation. Therefore, the test operation takes time, and since the signal is received in a decoded state as an analog signal, the only way to check the signal is to check the signal that has been attenuated or modified in the subscriber circuit, code decoding circuit, etc. Can not. That is, there are disadvantages in that the test requires time and it is not possible to accurately measure the output of the signal generator.

本発明の目的は、上述の従来の欠点を解決し、簡単かつ
正確に、信号発生器の出力の測定若しくは聴覚による確
認が可能なデジタル信号発生器試験方式を提供すること
にある。
SUMMARY OF THE INVENTION It is an object of the present invention to overcome the above-mentioned conventional drawbacks and to provide a digital signal generator testing method that allows the output of a signal generator to be easily and accurately measured or audibly confirmed.

本発明の試験方式は、デジタル可聴信号、デジタル多周
波信号等をそれぞれ発生させるデジタル信号発生器と、
これら信号発生器の出力信号を第1の多重化線路上の任
意のタイムスロットに送出する多重化装置と、前記第1
の多重化線路上の任意のタイムスロットと別の第2の多
重化線路上の任意のタイムスロットとを対応接続する時
分割スイッチと、前記第2の多重化線路上の任意のタイ
ムスロットを分離抽出する多重分離装置とを備えた時分
割交換機において、前記多重分離装置内に多重分離制御
回路の制御により前記第2の多重化線路上の特定のタイ
ムスロットを通過させる多重分離ゲートを備え、前記多
重分離制御回路は外部からのコマンドにより前記多重分
離ゲートを制御して前記第2の多重化線路上の特定のタ
イムスロットの信号をデジタル信号試験回路および又は
復号器に入力させることを特徴とする。
The test method of the present invention includes a digital signal generator that generates a digital audible signal, a digital multi-frequency signal, etc., and
a multiplexer that sends the output signals of these signal generators to arbitrary time slots on a first multiplex line;
a time division switch that connects any time slot on the multiplex line and any time slot on another second multiplex line, and separates any time slot on the second multiplex line; a time-division switching device for extracting a multiplexer and a demultiplexer, the multiplexer and demultiplexer including a demultiplexer gate that allows a specific time slot on the second multiplex line to pass through under the control of a demultiplexer control circuit; The demultiplexing control circuit is characterized in that it controls the demultiplexing gate by an external command to input the signal of a specific time slot on the second multiplexing line to a digital signal test circuit and/or a decoder. .

次に、本発明について、図面を参照して詳細に説明する
Next, the present invention will be explained in detail with reference to the drawings.

図は、本発明の一実施例を示すブロック図である。可聴
信号発生器1は、ダイヤルトーン、ビジートーン、リン
グバックトーン等の可聴信号をデジタル化して出力する
デジタル信号発生器であり、多周波信号発生器2はデジ
タル化された多周波信号を発生するデジタル信号発生器
である。これらのデジタル出力信号3A、3Bは、それ
ぞれゲー)4A、4Bを介して第1の多重化線路6上の
任意のタイムスロットに送出されて時分割スイッチ7に
供給される。多重化制御回路5はゲート4A。
The figure is a block diagram showing one embodiment of the present invention. The audible signal generator 1 is a digital signal generator that digitizes and outputs audible signals such as dial tones, busy tones, and ringback tones, and the multifrequency signal generator 2 is a digital signal generator that generates digitized multifrequency signals. It is a signal generator. These digital output signals 3A and 3B are sent out to arbitrary time slots on the first multiplex line 6 via gates 4A and 4B, respectively, and supplied to the time division switch 7. Multiplex control circuit 5 has gate 4A.

4Bの開閉制御により上記動作の制御を行なう。The above operation is controlled by opening/closing control of 4B.

多重化制御回路5およびゲート4A、4Bは多重化装置
3に内蔵されている。時分割スイッチ7は、第1の多重
化線路6上の任意のタイムスロット上の信号を第2の多
重化線路8上の任意のタイムスロットに対応接続するス
イッチであり、第2の多重化線路8上の各タイムスロッ
ト上の信号は、多重分離装置9において多重分離フリッ
プフロップ10Aにより、それぞれのタイムスロットに
対応した図示されない符号復号器、デジタルトランク等
に分離入力される。以上は、一般の時分割交換機の構成
と同様であるが、本実施例においては、多重分離装置9
内に、多重分離制御回路11の制御により前記第2の多
重化線路8上のあらかじめ定められた特定のタイムスロ
ットの信号を通過させる多重分離ゲートである多重分離
フリップフロップIOBを備えている。そして、多重分
離制御回路11は、多重分離ノリツブフロップIOAの
一般的な分離動作を制御すると共に、外部よりのコマン
ドにより前記多重分離フリップフロップ10)3を制御
して、前記特定のタイムスロット上の信号を、試験引込
線12を介して、デジタル信号試験回路13および復号
器14に入力させる。
Multiplex control circuit 5 and gates 4A and 4B are built into multiplexer 3. The time division switch 7 is a switch that connects a signal on an arbitrary time slot on the first multiplex line 6 to an arbitrary time slot on the second multiplex line 8. The signals on each of the time slots 8 are separated and input by a demultiplexing flip-flop 10A in the demultiplexing device 9 to a code decoder, digital trunk, etc. (not shown) corresponding to each time slot. The above is similar to the configuration of a general time division switch, but in this embodiment, the demultiplexer 9
A demultiplexing flip-flop IOB is provided therein, which is a demultiplexing gate that allows the signal of a predetermined specific time slot on the second multiplexing line 8 to pass through under the control of the demultiplexing control circuit 11. The demultiplexing control circuit 11 controls the general demultiplexing operation of the demultiplexing flip-flop IOA, and also controls the demultiplexing flip-flop 10) 3 based on an external command to The signal is input to the digital signal test circuit 13 and decoder 14 via the test lead-in line 12.

デジタル信号試験回路13は、入力デジタル信号の周波
数、レベル、送出周期等を測定し、かつ表示する機能を
有する。また復号器14は、入力デジタル信号をアナロ
グ信号に変換する。保守者は、試験回路13の表示によ
り、または、レシーバ15を用いヤ聴覚により、信号音
の確認ができる0 今、例えば、可聴信号発生器1の正常性を試験しようと
するとき、コマンド投入により多重化制御回路5は、多
重化ゲート4Aを制御して第1の多重化線路6上の特定
のタイムスロットにデジタル出力信号3Aを挿入する。
The digital signal test circuit 13 has a function of measuring and displaying the frequency, level, sending cycle, etc. of the input digital signal. The decoder 14 also converts the input digital signal into an analog signal. The maintenance person can check the signal sound by the display on the test circuit 13 or by hearing using the receiver 15. Now, for example, when trying to test the normality of the audible signal generator 1, the maintenance person can check the signal sound by inputting a command. The multiplexing control circuit 5 controls the multiplexing gate 4A to insert the digital output signal 3A into a specific time slot on the first multiplexing line 6.

該デジタル出力信号3Aは、時分割スイッチ7を介して
第2の多重化線路8上のあらかじめ定められた特定のタ
イムスロットに挿入される。そして、多重分離制御回路
11は、コマンドにより多重分離フリップフロップ10
Bを制御して上記特定のタイムスロット上の信号をデジ
タル信号試験回路13および復号器14に入力させる。
The digital output signal 3A is inserted into a predetermined specific time slot on the second multiplex line 8 via the time division switch 7. Then, the demultiplexing control circuit 11 controls the demultiplexing flip-flop 10 by a command.
B is controlled to input the signal on the specific time slot to the digital signal test circuit 13 and decoder 14.

すなわち、可聴信号発生器1の出力するデジタル出力信
号3Aは、デジタル信号試験回路13に入力される。試
験回路13は、該デジタル信号の周波数、レベル等を試
験し、表示する。また、復号器14の出力をレシーバ1
bにより確認することも可能である。本実施例において
は、デジタル信号発生回路の出力信号は、デジタル値の
ままで測定されるから減衰等の影響は受けず正確な測定
が可能となる効果がある。また、従来のように擬似呼を
発生させる作業が不要であり操作性が向上し簡単に試験
することができる。
That is, the digital output signal 3A output from the audible signal generator 1 is input to the digital signal test circuit 13. The test circuit 13 tests and displays the frequency, level, etc. of the digital signal. Also, the output of the decoder 14 is transmitted to the receiver 1.
It is also possible to confirm by b. In this embodiment, since the output signal of the digital signal generation circuit is measured as a digital value, it is not affected by attenuation, etc., and accurate measurement is possible. Further, unlike the conventional method, there is no need to generate a pseudo call, improving operability and making testing easier.

また、復号器により聴覚での確認も可能であるが、復号
器は本発明の必須の構成要件ではない。
Also, a decoder allows audible confirmation, but the decoder is not an essential component of the present invention.

図において、1・・・可聴信号発生器、2・・・多周波
信号発生器、3・・・多重化装置、3A、3B・・・デ
ジ・イツチ、8・・・第2の多重化線路、9・・・多重
分離装置、IOA、10・B・・・多重分離フリップフ
ロップ、11・・・多重分離制御回路、12・・・試験
引込線゛、13・・・デジタル信号試験回路、14・・
・復号器、15・・・レシーバ。
In the figure, 1...audible signal generator, 2...multifrequency signal generator, 3...multiplexer, 3A, 3B...digital switch, 8...second multiplex line , 9... Demultiplexing device, IOA, 10.B... Demultiplexing flip-flop, 11... Demultiplexing control circuit, 12... Test lead-in line, 13... Digital signal test circuit, 14...・
-Decoder, 15...receiver.

代理人 弁理士 住 1)俊 宗Agent: Patent attorney: 1) Sou Toshi

Claims (1)

【特許請求の範囲】[Claims] デジタル可聴信号、デジタル多周波信号等をそれぞれ発
生させるデジタル信号発生器と、これら信号発生器の出
力信号を第1“の多重化線路上の任意のタイムスロット
に送出する多重化装置と、前記第1の多重化線路上の任
意のタイムスロットと別の第2の多重化線路上の任意の
タイムスロットとを対応接続する時分割スイッチと、前
記第2の多重化線路上の任意のタイムスロットを分離抽
出する多重分離装置とを備えた時分割交換機において、
前記多重分離装置内に多重分離制御回路の制御により前
記第2の多重化線路上の特定のタイムスロットを通過さ
せる多重分離ゲートを備え、前記多重分離制御回路は外
部からのコマンドにより前記多重分離ゲートを制御して
前記第2の多重化線路上の特定のタイムスロットの信号
をデジタル信号試験回路および又は復号器に入力させる
ことを特徴とするデジタル信号発生器試験方式。
a digital signal generator that generates a digital audible signal, a digital multifrequency signal, etc.; a multiplexer that sends the output signals of these signal generators to any time slot on a first multiplex line; a time division switch that connects any time slot on one multiplex line and any time slot on another second multiplex line; and In a time division switch equipped with a demultiplexing device for separating and extracting,
The demultiplexing device includes a demultiplexing gate that allows a specific time slot on the second multiplexing line to pass under the control of a demultiplexing control circuit, and the demultiplexing control circuit controls the demultiplexing gate according to an external command. A digital signal generator testing method characterized in that the signal of a specific time slot on the second multiplexed line is inputted to a digital signal testing circuit and/or a decoder by controlling.
JP10998682A 1982-06-28 1982-06-28 System for testing digital signal generator Pending JPS592477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10998682A JPS592477A (en) 1982-06-28 1982-06-28 System for testing digital signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10998682A JPS592477A (en) 1982-06-28 1982-06-28 System for testing digital signal generator

Publications (1)

Publication Number Publication Date
JPS592477A true JPS592477A (en) 1984-01-09

Family

ID=14524180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10998682A Pending JPS592477A (en) 1982-06-28 1982-06-28 System for testing digital signal generator

Country Status (1)

Country Link
JP (1) JPS592477A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57132545A (en) * 1981-02-09 1982-08-16 Sanyo Electric Co Ltd Composition for absorption refrigerator
JPH02100556A (en) * 1988-10-07 1990-04-12 Fujitsu Ltd Network tester

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57132545A (en) * 1981-02-09 1982-08-16 Sanyo Electric Co Ltd Composition for absorption refrigerator
JPH0239556B2 (en) * 1981-02-09 1990-09-06 Sanyo Denki Kk
JPH02100556A (en) * 1988-10-07 1990-04-12 Fujitsu Ltd Network tester

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