JPS5923875A - Dry etching method - Google Patents

Dry etching method

Info

Publication number
JPS5923875A
JPS5923875A JP13412482A JP13412482A JPS5923875A JP S5923875 A JPS5923875 A JP S5923875A JP 13412482 A JP13412482 A JP 13412482A JP 13412482 A JP13412482 A JP 13412482A JP S5923875 A JPS5923875 A JP S5923875A
Authority
JP
Japan
Prior art keywords
etching
silicon
sif4
dry
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13412482A
Other languages
Japanese (ja)
Other versions
JPS6231071B2 (en
Inventor
Yoshitsugu Nishimoto
西本 佳嗣
Shingo Kadomura
新吾 門村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP13412482A priority Critical patent/JPS5923875A/en
Publication of JPS5923875A publication Critical patent/JPS5923875A/en
Publication of JPS6231071B2 publication Critical patent/JPS6231071B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To enable etching in the state of suppressing the contamination and damage of an Si object to be treated as far as possible and to clean the contaminated and damaged surface in the dry etching stage of said object, by using a gaseous mixture composed of SiF4 and H2. CONSTITUTION:Resist 1 is deposited on an SiO2 film 2; thereafter, the film 2 is selectively etched by reactive ion etching in the case of, for example, cleaning the surface of an Si substrate 3. Damages are formed on said surface in this stage. Thereupon, the surface is dry etched with a gaseous mixture composed of SiF4 and H2 and is then subjected to an O2 plasma treatment to remove a polymer layer and the resist 1; further the substrate is subjected to a soln. treatment. An SiO2 film 5 is selectively deposited on an Si substrate 4 and is etched with a gaseous mixture composed of SiF4 and H2 in selective etching of an Si type.

Description

【発明の詳細な説明】 この発明は被処理物をドライ、エツチングする方法に関
し1時にドライエツチングにより引き起こされる汚染や
損傷の問題を解消し得るようにしたものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for dry etching a workpiece, and is capable of solving the problems of contamination and damage caused by dry etching.

一般にプラズマのエツチング、RIE(リアクティブイ
オンエツチング)、RIM(リアクティブイオンミリン
グ)等の気体放電を利用して半導体(Si 、Ga、A
s等)や薄膜等のドライエツチングを行なう場合、半導
体や薄膜の表面又は表面近傍の内部に汚染や照射損傷を
生じ、この後これら汚染やJp4傷を残したままでLS
I等を作成すれば電気的特性の劣化を生じる。これはト
ラップ準位が形成されたり、短絡が引き起こされたりす
るためである。このことは周知の事実である。このよう
な汚染及び照射損傷を詳しく分類すれば次のようになる
Generally, semiconductors (Si, Ga, A
When performing dry etching on semiconductors and thin films, contamination and irradiation damage occur on the surface of the semiconductor or thin film, or within the vicinity of the surface.
If I or the like is created, the electrical characteristics will deteriorate. This is because a trap level is formed or a short circuit is caused. This is a well-known fact. The detailed classification of such contamination and irradiation damage is as follows.

■ 表面に付着する高分子フィルム層。■ Polymer film layer that adheres to the surface.

これは主にエツチングに使用するガスの成分元素がプラ
ズマのエネルギにより重合されてできたものと考えられ
る。
This is thought to be mainly due to the polymerization of the constituent elements of the gas used for etching due to the energy of the plasma.

■ 半導体や薄膜の表面近くの内部に没入する不純物元
素。
■ Impurity elements that penetrate into the interior of semiconductors and thin films near their surfaces.

これは第1にエツチングガスの構成元素がプラズマ中で
イオン化され陰極降下電圧等の放電内部電界で加速され
入射されたものである。第2にエツチング装置の構成物
質である重金属(Fe、Co、Ni 、AQ等)がスパ
ッタリングにより入射させられたものである。
First, the constituent elements of the etching gas are ionized in the plasma, accelerated by the discharge internal electric field such as the cathode drop voltage, and then injected into the plasma. Second, heavy metals (Fe, Co, Ni, AQ, etc.), which are constituent materials of the etching apparatus, are made incident by sputtering.

■ 半導体の表面近くの内部に生じる結晶欠陥。■Crystal defects that occur inside the semiconductor near its surface.

これはプラズマ中で生成された荷1ft粒子(イオン及
び電子)、紫外線、X線及びチャンバの構成物質である
スパッタ元型の入射等によるものである。
This is due to the incidence of charged 1ft particles (ions and electrons) generated in the plasma, ultraviolet rays, X-rays, and the sputtering mold that is the constituent material of the chamber.

このような汚染や照射JJt傷に対してドライ処理によ
りクリーニングを行なうにはo2プラズマ処理が考えら
れる。このプラズマ処理では上述■の(Cx、Fy)系
の高分子フィルムをプラズマ中で酸化させ除去する。こ
のプラズマ処理はレジストのアッシングを兼ねて用いら
れるが完全なりリーニング方法としては実現されていな
い。又上述■、■の汚染及び損傷に対しては有効なりリ
ーニング方法が提供されていない。
To clean such contamination and irradiation JJt scratches by dry treatment, O2 plasma treatment can be considered. In this plasma treatment, the above-mentioned (Cx, Fy) polymer film is oxidized in plasma and removed. Although this plasma treatment is also used for resist ashing, it has not been realized as a complete leaning method. Furthermore, no effective cleaning method has been provided for the above-mentioned contamination and damage.

この発明はこのような事情を考慮してなされたものであ
り、汚染や損傷を極カ押えた状態で5iOzや5I3N
t4等を下地材料又はマスクとして被処理物をエツチン
グし得ると共に他のエツチング処理で汚染や損傷を受け
た表面をドライクリーニングする場合にも好適なドライ
エツチング方法を提供することを目的としている。
This invention was made in consideration of these circumstances, and it is possible to produce 5iOz and 5I3N while minimizing contamination and damage.
It is an object of the present invention to provide a dry etching method which is capable of etching an object to be processed using etching material such as T4 as a base material or mask, and which is also suitable for dry cleaning a surface contaminated or damaged by other etching processes.

この発明ではこのような目的を達成するためにCF4と
Hzとの混合ガスでシリコン系をエツチングするように
している。
In order to achieve this purpose, the present invention etches silicon based material using a mixed gas of CF4 and Hz.

シリコン系としては単結晶シリコン及び多結晶シリコン
が考えられる。
As silicon-based materials, single crystal silicon and polycrystalline silicon can be considered.

被処理面としてはドライクリーニングを施すべき表面が
第1に考えられる。即ち仙のエツチング処理により汚染
や損傷を受ゆた表面をこのエツチング処理によりドライ
クリーニングするのである。
The first surface to be treated is the surface to be dry cleaned. That is, surfaces that have been contaminated or damaged by the etching process are dry cleaned by this etching process.

第2にS i02基体又はS i 3N4の薄膜を下地
材料又はマスクとしてシリコン系をエツチングすること
が考えられる。
A second possibility is to etch a silicon-based material using a Si02 substrate or a thin film of Si3N4 as a base material or mask.

ドライクリーニングでは、たとえば第1図に示す処理が
行われる。即ち、レジスト(1)を8102膜(2)上
に被着(第1図へ)したのち)ロE″″C:5lOz膜
の選択エツチングを行う。この場合、第1図Bに散点で
示すように1シリコシ基体(3)の表面に損傷が形成さ
れる。そこで、本発明による5IF4とHzとの混合ガ
スによるドライクリーニングジ行い(第1図C)、この
のち02プラズマ処理を行って高分子層やレジメ) (
1)を除去しく第1図D)、さらに溶液処理を行う(第
1図E)。こののら、次の工程に移1jする。
In dry cleaning, for example, the process shown in FIG. 1 is performed. That is, after the resist (1) is deposited on the 8102 film (2) (see FIG. 1), selective etching of the 51Oz film is performed. In this case, damage is formed on the surface of the silicon substrate (3) as shown by scattered dots in FIG. 1B. Therefore, dry cleaning was performed using a mixed gas of 5IF4 and Hz according to the present invention (Fig. 1C), and then 02 plasma treatment was performed to remove the polymer layer and the regimen) (
1) is removed (FIG. 1D), and then subjected to solution treatment (FIG. 1E). After this, move on to the next step 1j.

シリコン系の選択エツチングでは、たとえば第2図に示
す処理が行われる。即、ち、シリコン糸体(4)上に8
102膜(5)を選択被着しく第2図A)、この上から
SiF4とIIzとの混合ガスでエツチングを行うので
ある(第2図B)。
In silicon-based selective etching, for example, the process shown in FIG. 2 is performed. That is, 8 on the silicon thread body (4)
The 102 film (5) is selectively deposited (FIG. 2A), and etched thereon with a mixed gas of SiF4 and IIz (FIG. 2B).

混合ガスの混合比はトータルの混合ガスに対してHzな
20〜80容量%の範囲で添加する。特にシリコン系を
5102やS 13.N4に対して選択エツチングする
時には、これを約50容量%とすることが好ましい。
The mixed gas is added at a mixing ratio of 20 to 80% by volume based on the total mixed gas. In particular, silicon-based products such as 5102 and S13. When selectively etching with respect to N4, it is preferable to set this to about 50% by volume.

装置としては円筒形や平行平板電極形のプラズマエツチ
ング装置やILIB装置等を用いることができる。特に
S i 3N4等をマスクとしてシリコン系をエツチン
グする時にはサイドエツチングを減少させるためにRI
E装置等を用いることが好ましい。
As the apparatus, a cylindrical or parallel plate electrode type plasma etching apparatus, an ILIB apparatus, or the like can be used. In particular, when etching silicon based materials using Si3N4 etc. as a mask, RI is used to reduce side etching.
It is preferable to use an E device or the like.

本発明によるドライエツチング方法によれば汚染や照射
損傷の無いエツチングを行なえる。又他のエツチング処
理により汚染や照射損傷のあった被処理面にドライクリ
ーニングを有効に行なうことができる。これは本発明で
は炭素を用いないこと、Siの被着が起ること等のため
であると思われる。即ち従前のCFA系ガスでSiをエ
ツチングした時に生じるSi中の汚染元素をIMMAで
分析すると汚染元素として主にCIFIが検出される。
According to the dry etching method of the present invention, etching can be performed without contamination or radiation damage. Furthermore, dry cleaning can be effectively performed on a surface to be treated that has been contaminated or damaged by radiation due to other etching treatments. This is thought to be due to the fact that carbon is not used in the present invention and Si is deposited. That is, when contaminant elements in Si produced when etching Si with a conventional CFA-based gas are analyzed by IMMA, CIFI is mainly detected as the contaminant element.

本発明のようにSiF4系のガスを使用すれば半導体装
置に有害なCの汚染を防止できる。又本例で用いるSi
F+はグロー放電中では分解しやす<、31の被着が生
じやすい。太陽電池用のアモルファスシリコン膜はこれ
を利用して形成されるものである。このようなシリコン
の被着により損傷が復元されるものと考えられる。次に
例を挙げてこの発明について更に説明する。
If SiF4-based gas is used as in the present invention, it is possible to prevent C contamination that is harmful to semiconductor devices. Also, Si used in this example
F+ is easily decomposed during glow discharge, and deposition of 31 is likely to occur. Amorphous silicon films for solar cells are formed using this. It is believed that the damage is restored by such adhesion of silicon. Next, the present invention will be further explained with reference to examples.

〔例1〕 ここでは装置としてエッチチャンネルを有する円筒形の
プラズマエツチング装置を用いる。そして反応ガスとし
℃のSiF4及びHzの混合ガスに付きH2添加量を変
化させた時の各種処理面のエツチング特性を測定した。
[Example 1] Here, a cylindrical plasma etching device having an etch channel is used. Then, the etching characteristics of various treated surfaces were measured when the amount of H2 added was varied using a mixed gas of SiF4 at .degree. C. and Hz as a reaction gas.

測定東件は圧力0.8トル、高周波電力200Wである
。被エツチング物としては単結晶P形シリコン(エツチ
ング面7 (111)面とする)、多結晶シリコン、P
注入多結晶シリコン、低圧CVDで形成されたS i 
3N4及び熱酸化5i(Jzを用いた。これら被エツチ
ング物のエツチング惠をそれぞれ第3図にA、B、C,
D、Eで示す。
The measurement conditions were a pressure of 0.8 torr and a high frequency power of 200W. The objects to be etched include single-crystal P-type silicon (etching surface 7 is (111) plane), polycrystalline silicon, P-type silicon, and
Implanted polycrystalline silicon, Si formed by low pressure CVD
3N4 and thermal oxidation 5i (Jz) were used. The etching effects of these etching objects are shown in Figure 3 as A, B, C,
Indicated by D and E.

この第3図から明らかなようにSiF4のみの時はSi
 3N4 (D)がエツチングされ、他方5I02°、
Si等はほとんどエツチングされない。又、観察により
単結晶シリコンの表面荒れが発生した。H2の添加量を
増加して行くとシリコン系即ち単結晶シリコン、多結晶
シリコン、P注入多結晶シリコン等のエツチング率が上
昇して行く。そしてHzの添加量が20〜80容量%の
範囲ではこれらシリコン系のエツチング率が5iOz 
、 Si3N<に対し非常に大きくなる。特に1゛I2
添加量が約50容量%の時には5iOz。
As is clear from this figure 3, when only SiF4 is used, Si
3N4 (D) is etched, while 5I02°,
Si and the like are hardly etched. Furthermore, observation revealed that surface roughness of the single crystal silicon occurred. As the amount of H2 added increases, the etching rate of silicon-based materials, ie, single crystal silicon, polycrystalline silicon, P-implanted polycrystalline silicon, etc. increases. When the addition amount of Hz is in the range of 20 to 80% by volume, the etching rate of these silicon-based materials is 5iOz.
, becomes very large for Si3N<. Especially 1゛I2
When the amount added is about 50% by volume, it is 5 iOz.

Si 3N4はほとんどエツチングされないのに対し、
単結晶シリコン、多結晶シリコン、P注入多結晶シリコ
ンのエツチング率は150〜200 l/minのピー
クに達し、St /5iOz 、 Si /Si:+N
4のエツチング速度比は数十又はそれ以上と非常に太き
(5iOz及びSi3N4に対してシリコン系の高選択
性が示される。又観割によればシリコン系の表面荒れは
ない。
Whereas Si 3N4 is hardly etched,
The etching rate of single crystal silicon, polycrystalline silicon, and P-implanted polycrystalline silicon reaches a peak of 150-200 l/min, St /5iOz, Si /Si: +N
The etching rate ratio of No. 4 is very large, several tens or more (high selectivity of silicon based on 5iOz and Si3N4 is shown. Also, according to the evaluation, there is no surface roughness of silicon based).

このことから本発明によるドライエツチング方法を5i
02やSi3N4をマスク又は下地′4I料としシリコ
ン系のエツチングを行7.cう場合に適用できることが
解る。そしてこの場合には汚染や照射損傷が極めて少な
い。
From this, the dry etching method according to the present invention can be applied to 5i.
7. Perform silicon-based etching using 02 or Si3N4 as a mask or base '4I material.7. It can be seen that it can be applied when In this case, contamination and radiation damage are extremely low.

〔例2〕 ここではバイポーラトランジスタ等の電極コンタクト窓
明は工程でシリコン基体上の8102層をILIEでエ
ツチングした後ドライクリーニングを行なった。
[Example 2] Here, the electrode contact window of a bipolar transistor, etc. was formed by etching the 8102 layer on the silicon substrate by ILIE in the process and then dry cleaning it.

SiF4及び1(2の混合ガスにおし少るHzの添加量
としては約50容t%となるようにした。そしてAs拡
散層、AJ他電極のコンタクト抵抗を求めた。コンタク
トホールの面積としては約2〜100I血2の範囲に亘
って測定を行なった。このコンタクト抵抗及びギのばら
つき・中−%−(その指標としてσ/Tt(%)を用い
た。ここでσはコンタクト抵抗値の標準偏差、πは測定
したコンタクト抵抗の平均値である。)の測定結果を第
4図及び第5図にそれぞれAで示す。この測定結果は従
前のものに比べ極めて良好なものであった。
The small amount of Hz added to the mixed gas of SiF4 and 1 (2) was set to about 50% by volume.Then, the contact resistance of the As diffusion layer, AJ and other electrodes was determined.The area of the contact hole was The measurement was carried out over a range of about 2 to 100I blood 2.The variation of this contact resistance and force was used as an index of σ/Tt (%).Here, σ is the contact resistance value. The standard deviation of π is the average value of the measured contact resistance.) The measurement results are shown as A in Figures 4 and 5, respectively.This measurement result was extremely good compared to the previous one. .

一般にシリコン基体上のS 102層をRIEでエツチ
ングすると汚染及び照射損傷が発生し、このためAs拡
散層とAg電極とのコンタクト抵抗が増大し、又コンタ
クト抵抗値に大きなばらつきが生じる。従前もドライク
リーニング或いはウェットクリーニングを行なっていた
が充分ではなかった。
Generally, when an S102 layer on a silicon substrate is etched by RIE, contamination and radiation damage occur, which increases the contact resistance between the As diffusion layer and the Ag electrode, and also causes large variations in the contact resistance value. Previously, dry cleaning or wet cleaning had been carried out, but it was not sufficient.

第4図及び第5図にBで示すものは酸(H2SO4及び
HNO4)による煮沸及びライトエツチングによって溶
液処理を行なったものであり、Cで示すものはCF4 
、 Ar及び02によるドライクリーニングを施したも
のである。第4図及び第5図にB、Cで示すこれら従前
の物に比らべ本発明によれば極めて良好な結果を得るこ
とができる。
In Figs. 4 and 5, those indicated by B were solution-treated by boiling with acids (H2SO4 and HNO4) and light etching, and those indicated by C were CF4.
, Ar and 02 dry cleaning were performed. Compared to these conventional products shown by B and C in FIGS. 4 and 5, the present invention provides extremely good results.

以上述べたようにこの発明によれば5102やSt 3
N4等を下地材料又はマスクとしてシリコン系の選択エ
ツチングを行ない、しかも汚染や照射損傷を極力押える
ことができる。そしてこの発明によるドライエツチング
方法を他のエツチング処理後のドライクリーニングに用
いれば極めて実効がある。
As described above, according to the present invention, 5102 and St 3
Silicon-based selective etching can be performed using N4 or the like as a base material or mask, and contamination and irradiation damage can be suppressed as much as possible. The dry etching method according to the present invention is extremely effective when used for dry cleaning after other etching treatments.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は本発明の説明に供する断面図、第
3図〜第5図は同様のグラフである。 同      松 隈 秀 盛H1i、、ヂ、・9.・
1】び′ 第3図 〃2 カパス の 容 f /ぐ一セ〉ト手続ネili
 JE摺: 昭和57年10月22日 昭和57年特許願第134124号 2°光1す1′1′2″+IF′    ドライーツチ
ング方法:3. ?di止をする考 事件との関係   特許出願人 住所 東以I’l1品用区北品用6丁E+7番:35号
名称 C!l!:)  ソ ニ − 抹ゴ(会社代表取
ti’l:役 大 賀 pll  )、fL4、代理人 住 所 東京都新宿区西新宿1丁目8番1号TIEL 
03−343−5821tl15  (新宅ビル)(i
、 ?+li市に、Lり増加する発明の数7、袖11−
のス1象      明細−の発明の詳細な説明の瘤(
1)  明細書の第5頁19行の「stの被着が起こる
こと」を「Siの被着が生ずるプラズマ条件とSiのエ
ツチングが生ずるプラズマ条件との境界であるプラズマ
状態を作るような条件を選んでいること」に訂正する。 (2)同第6頁2行の「CIFl」を「C及びF」に訂
正する。 (3)  同第6頁7〜9行の「このよ5な曇−考えら
れる。」を削除する。 以上 41
1 and 2 are cross-sectional views for explaining the present invention, and FIGS. 3 to 5 are similar graphs. Same Hide Matsukuma H1i,,ヂ,・9.・
1) Fig. 3 2 Capas contents f / set procedure Neili
JE Printing: October 22, 1981 Patent Application No. 134124 2° Light 1 1'1'2'' + IF' Dry cutting method: 3. Relationship with the case for stopping ?di Patent application Person address: 6-chome E+7: 35, Higashii I'l1 product ward, No. 35 Name: C!l!:) Soni - Macago (company representative director ti'l: role Ohga pll), fL4, agent Address: TIEL, 1-8-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo
03-343-5821tl15 (Shintaku Building) (i
, ? +The number of inventions increasing by 7 in the city, sleeves 11-
Part 1 of the detailed description of the invention (
1) In page 5, line 19 of the specification, ``occurrence of deposition of st'' is defined as ``conditions that create a plasma state that is the boundary between plasma conditions that cause deposition of Si and plasma conditions that cause etching of Si. Please correct it to ``I have selected ``. (2) Correct "CIFl" in line 2 of page 6 to "C and F". (3) Delete "This is 5 clouds - I can think of it." on page 6, lines 7-9. Above 41

Claims (1)

【特許請求の範囲】[Claims] SiF4及びH2の混合ガスで被処理物のエツチングを
行なうドライエツチング方法。
A dry etching method in which a workpiece is etched using a mixed gas of SiF4 and H2.
JP13412482A 1982-07-30 1982-07-30 Dry etching method Granted JPS5923875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13412482A JPS5923875A (en) 1982-07-30 1982-07-30 Dry etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13412482A JPS5923875A (en) 1982-07-30 1982-07-30 Dry etching method

Publications (2)

Publication Number Publication Date
JPS5923875A true JPS5923875A (en) 1984-02-07
JPS6231071B2 JPS6231071B2 (en) 1987-07-06

Family

ID=15121020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13412482A Granted JPS5923875A (en) 1982-07-30 1982-07-30 Dry etching method

Country Status (1)

Country Link
JP (1) JPS5923875A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639121A (en) * 1986-06-30 1988-01-14 Toshiba Corp Dry etching
EP1619269A2 (en) * 2004-07-23 2006-01-25 Air Products And Chemicals, Inc. Method for enhancing fluorine utilization

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63183077U (en) * 1987-05-19 1988-11-25
JPH01257439A (en) * 1987-07-17 1989-10-13 Nippon Flour Mills Co Ltd Cooking of pasta and noodle and heat-resistant package for cooking same and packaged noodle

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5565364A (en) * 1978-11-08 1980-05-16 Toshiba Corp Etching method
JPS56144543A (en) * 1980-03-17 1981-11-10 Ibm Method of manufacturing semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5565364A (en) * 1978-11-08 1980-05-16 Toshiba Corp Etching method
JPS56144543A (en) * 1980-03-17 1981-11-10 Ibm Method of manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639121A (en) * 1986-06-30 1988-01-14 Toshiba Corp Dry etching
EP1619269A2 (en) * 2004-07-23 2006-01-25 Air Products And Chemicals, Inc. Method for enhancing fluorine utilization
EP1619269A3 (en) * 2004-07-23 2006-11-08 Air Products And Chemicals, Inc. Method for enhancing fluorine utilization
KR100760891B1 (en) 2004-07-23 2007-09-27 에어 프로덕츠 앤드 케미칼스, 인코오포레이티드 Method for enhancing fluorine utilization

Also Published As

Publication number Publication date
JPS6231071B2 (en) 1987-07-06

Similar Documents

Publication Publication Date Title
US20060201911A1 (en) Methods of etching photoresist on substrates
US20080182422A1 (en) Methods of etching photoresist on substrates
US8716143B1 (en) Plasma based photoresist removal system for cleaning post ash residue
US11854766B2 (en) DC bias in plasma process
JP2001514800A (en) Method and apparatus for removing photoresist mask defects in a plasma reactor
TW200809959A (en) Photoresist stripping chamber and methods of etching photoresist on substrates
US20040214448A1 (en) Method of ashing a photoresist
US20040211517A1 (en) Method of etching with NH3 and fluorine chemistries
Hess et al. Plasma stripping, cleaning, and surface conditioning
JP3593195B2 (en) Method for manufacturing SiC single crystal substrate
JPS5923875A (en) Dry etching method
CN113614891A (en) Dry etching method and method for manufacturing semiconductor device
JP4124675B2 (en) Method and apparatus for low-temperature oxidation of silicon wafer
Yavas et al. Laser cleaning of field emitter arrays for enhanced electron emission
JP3351003B2 (en) Method for manufacturing semiconductor device
Ichihashi et al. Effects of thermal annealing for restoration of UV irradiation damage during plasma etching processes
Tang et al. Process damage assessment of a low energy inductively coupled plasma-based neutral source
KR100511918B1 (en) The Apparatus for processing wafer edge
JPS6030098B2 (en) Spatsuta etching method
JP6372436B2 (en) Method for manufacturing semiconductor device
TW541358B (en) Method for dry cleaning metal etching chamber
JPS59214226A (en) Etching method
Ang et al. Sputter-etching and plasma effects on the electrical properties of titanium nitride contacts on n-type silicon
JP3357951B2 (en) Dry etching method
Takai et al. Laser Cleaning of Silicon Field Emitter Array