JPS592348B2 - Pulse response waveform measurement method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse response measurement method that allows highly accurate and automatic pulse response testing of a circuit under test by repeatedly inputting a waveform.

In testing the characteristics of semiconductor devices, a pulse response test is one of the most important tests, in which a high-speed folded pulse is supplied as an input signal to an input terminal, and a pulse response waveform outputted from an output terminal is observed and measured. In the above pulse response test, the response waveform often has a short period and a steeply sloped part, so conventionally the response waveform output from the output end of the semiconductor device is observed using a direct viewing device such as an oscilloscope. Alternatively, the above response waveform can be converted into a digital quantity using an analog circuit such as a sample hold circuit, stored temporarily, and then converted back to an analog quantity as necessary for observation and measurement using a direct viewing device such as an oscilloscope. A method is being adopted to do so. In all of the conventional measurement methods described above, the waveform of the response signal is visually observed, so the response signal cannot be analyzed with high precision, and moreover, the measurement test requires a lot of time. Also,
In order to improve measurement accuracy, it is necessary to use a high-speed direct viewing device. Generally, high-speed direct-viewing equipment is very expensive, and even if high-speed direct-viewing equipment is used, there is a limit to the accuracy of measurement because final judgments are made by visual inspection. The present invention has been made in consideration of the above circumstances, and is a method for measuring pulse response waveforms that enables highly accurate and automatic pulse response measurement of a circuit under test, and that allows the device configuration to be realized at a low cost. The goal is to provide a method.

A peak value detection circuit according to an embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, T1 is an input terminal, and this input terminal T1 is connected to the output terminal of a circuit under test, such as a semiconductor device under test (not shown). Further, the input terminal T1 is connected to an input terminal of a level comparison circuit 2 via a first buffer amplifier 1. The other input end of the level comparison circuit 2 is connected to the output end of a reference level generation circuit, which will be described later. The output terminal of the level comparison circuit 2 is connected in parallel to each AND gate of a first gate circuit 3 consisting of n AND gates 31, 32, . . . 3n for the first to nth digits. Ru. The other input terminals of each of the n AND gates 31, 32, . n AND gates 31 and 32 forming the first gate circuit 3
, . . 3n are connected in parallel to the output terminals of the first to nth digits of a counter circuit, which will be described later. The output terminal of the first gate circuit 3 is connected to a first memory circuit 4 consisting of, for example, n R-S flip-flops.
is connected in parallel to the input terminal of. This first memory circuit 4
The output terminal of is connected in parallel to the input terminal of the second memory circuit 5, and the n OR gates 6 of the first to nth digits are connected in parallel to the input terminal of the second memory circuit 5.
1, 62, . . . 6n are connected in parallel to the respective OR gates of the second gate circuit 6. 7 is a counter circuit consisting of, for example, an n-ary ring counter, and n output terminals of the first to nth digits of this counter circuit 7 are connected to the n OR gates constituting the second gate circuit 6. AND gates 31 and 32 of each digit are connected in parallel to the input terminals and constitute the first gate circuit 3;
, . . . 3n are connected in parallel to the input terminals.

The output terminals of each digit of the second gate circuit 6 are connected in parallel to the input terminals of the first to nth digits of the reference level generating circuit 8. Note that this reference level generating circuit 8 will be described in detail later. The output terminal of the reference level generating circuit 8 is
It is connected to the input terminal of the level comparison circuit 2, and is also connected to the output terminal TOl via the second buffer amplifier 9. 10 is a control circuit, and a clock pulse input terminal of this control circuit 10 is connected to an input terminal T2.

Further, the set terminals of the control circuit 10, the first memory circuit 4, and the counter circuit 7 are collectively connected to the input terminal T3. Further, each output terminal of the first to nth digits of the second memory circuit 5 is connected to an output terminal T.
O2-1? TO2-2?゜゜゜O connected to T02-n FIG. 2 is a circuit configuration diagram showing an example of the reference level generation circuit 8, in which the output terminals of the first to nth digits of the second gate circuit 6 are connected in parallel. Input terminals TlO-1 to TlO-. are connected to each. The above input terminals TlO-1 to TlO
−. have n C-MOS inverters 211, 212, 211, 212, .
...21n is connected. Furthermore, each of the C-MOS inverters 211, 212, .
n-1 resistors 231 to 23 with a resistance value of 1/2 of n
. .about.1 series circuits are sequentially connected to the foremost point a and each connection point b... And the foremost point a, that is, the resistance 2
A connection point between the resistor 31 and the resistor 221 is connected to the output terminal TOIO. In addition, the n-1 resistors 23, to 23n-
The last point C of one series circuit is grounded via a resistor 24 having the same resistance value as the resistors 221 to 22n. Next, the operation of the circuit connected and configured as described above will be explained with reference to FIGS. 3 and 4.

Here, for example, FIG. 3 AVC. An input pulse PG having a repetitive waveform as shown in FIG. A case will be described in which the peak level Vp is detected at O. First, an input pulse PG as shown in FIG. 4a outputted from a pulse generator (not shown) is input to a semiconductor device under test (not shown). At this time, the semiconductor device under test generates a response signal V as shown in FIG. 4b. outputs. The response signal o is sent from the input terminal T1 to the first buffer amplifier 1.
The signal is input to the input terminal of the level comparator circuit 2 via. On the other hand, the pulse generator outputs an input clock pulse P-Gc as shown in FIG. 4c, which is synchronized with the input pulse P-G. Next, the input clock pulse P-Gc output from the pulse generator is sent to the control circuit 10 via the input terminal T2.
is input. The control circuit 10 inputs the input clock pulses P·Gc to the counter circuit 7, and also inputs the gate control signals G·Gc having a repetitive waveform as shown in FIG. 4e.
P is input to each input terminal of AND gates 31, 32, . The counter circuit 7 to which the input clock pulses P and Gc are input receives the input clock pulses P and Gc.
are counted sequentially. First, the output terminal of the first digit among the n output terminals of the counter circuit 7 is at the logic level 1F' for a predetermined period of time as shown in FIG. 4D. Therefore, among the n OR gates constituting the second gate circuit 6, the input terminal of the first digit OR gate 6 also becomes the logic level "B", and the n OR gates constituting the first gate circuit 3 Among the AND gates, the input terminal of the first digit AND gate 30 also has a logic level of 1. Therefore, the first digit OR gate 6,
The output terminal of the reference level generating circuit 8 shown in FIG.
1st digit C-MOS inverter 2 connected to lO-1
1, VC input signal is given. Therefore, at this time, the first digit C-MOS inverter 211 outputs its power supply voltage Vs. Here, for example, the resistor 221~
22n trigram and resistance 24 value is 200KΩ, resistance 231~
When the value of 23n is 100KΩ, the output terminal TOIO
V.C. produces a voltage level of 1/2Vs. i.e. 1
/2Vs is input to the level comparison circuit 2VC as a reference level. The level comparison circuit 2 compares the response signal VO repeatedly inputted via the input terminal T1 with a reference level of 1/2Vs inputted from the reference level generation circuit 8. As shown in FIG. 4 TO-T1, the reference level 1/2Vs is the response signal V. ．． If the peak level Vp is within the range of the peak level Vp of gate circuit 3
are input in parallel to each AND gate 3, to 3n. At this time, only the AND gate 31VC of the first digit is input with the logic level 1V of the counter circuit 7, so only the AND gate 3 of the first digit is input to the fourth
A signal of logic level "B" as shown in FIG. f1 is output.
The first memory circuit 4 includes the AND gate 3 of the first digit.
The signal of logic level ``F'' outputted by 1 is temporarily stored, and the signal of logic level ``F'' is output from its output terminal. Logic level "1" output from the first memory circuit 4
The signal is transmitted to the second memory circuit 5 and the second gate circuit 6.
input to the OR gate 61 of the first digit. Therefore, the input terminal TlO-1 of the first digit of the reference level generation circuit 8 is always kept at the logic level "1" after this. Also, the second storage circuit 5 stores the input terminal of the logic level "1". Memorize the signal once. Next, the counter circuit 7 counts the input clock pulses P-Gc supplied from the control circuit 10, and this time, from the output terminal of the second digit, as shown in FIG. Output a signal. The logic level "1" signal outputted from the output terminal of the second digit of the counter circuit 7 is input to the AND gate 32 of the second digit of the first gate circuit 3, and also inputs to the AND gate 32 of the second digit of the first gate circuit 3. Input to 2-digit OR gate 62. The logic level repeat signal input to the second digit OR gate 62 of the second gate circuit is applied to the second digit input terminal TlO-2 of the reference level generating circuit 8. At this time, the reference level generating circuit 8 includes the first,
An input signal is applied to both input terminals TlO-1 and T10-2 of the second digit. Therefore, the first and second digits C-M
The OS inverters 211 and 212 operate, and the output terminal TO
In addition to the above 1/2Vs level, lOVC is 1/2×1/
2Vs or 1/4Vs level occurs, and overall (1
/2+1/4)Vs level is generated. The reference level of (1/2+1/4)Vs is input to the level comparison circuit 2VC. The level comparison circuit 2 receives the response signal VO repeatedly inputted via the input terminal T1;
(1/2+1/
4) Compare the reference level Vs with the reference level, and if the reference level is within the range of the peak level Vp of the response signal VO, the
A signal of logic level "1" is output during the period shown as 2 to T3.The signal output from the level comparison circuit 2 is outputted to each of the AND gates 31 to 31 of the second gate circuit 3.
3n in parallel. At this time, since the signal from the counter circuit 7 is input only to the AND gate 32 of the second digit, only the AND gate 32 of the second digit inputs the logic level to the first memory circuit 4 as shown in FIG. 4 F2. Outputs the signal of ゛. The first memory circuit 4 temporarily stores the logic level "1" signal output by the AND gate 32 of the second digit, and outputs it from its output terminal. The signal is input to the second storage circuit 5 and the second digit OR gate 62 of the second gate circuit 6.Therefore, the second digit input terminal TlO-2 of the reference level generation circuit 8 is always The second storage circuit 5 temporarily stores the input signal. If the reference level is equal to or higher than the peak level Vp of the response signal VO, the output terminal of the level comparison circuit 1 remains at logic level 1 ``''. That is, at this time, the output terminal of the AND gate remains at logic level 3'05'. Therefore, the input terminal of the corresponding digit of the reference level generation circuit 8 is kept at the logic level "O".Similarly, every time the counter circuit 7 counts the input clock pulses P-Gc, the reference level generation circuit 8 sequentially outputs n different reference levels to the level comparison circuit 2. Therefore, the fourth
After passing through FIG. T4, the reference level generation circuit 8 finally generates a level Vs(1/21b1+1/22b2)+...+ corresponding to the peak level VplfC of the response signal VO.
1/2nbn). However, b1 to Bn are signals of logic level 3'' or ``'' applied to the input terminal of the reference level generating circuit 8. A level corresponding to the peak level Vp is applied to the output terminal TOl via the second buffer amplifier 9. Each output terminal TO, -, ~TO2- of the second memory circuit 5. , digital information of the pick level Vp is output. In the above circuit, the peak level Vp can be detected with higher accuracy by increasing the number of bits n of the first and second gate circuits 3, 6, counter circuit 7, etc. as necessary.

Note that the resolution of the peak level is expressed as 1/2n. Furthermore, since no analog memory or the like is used, high-speed detection is possible. Furthermore, the first and second gate circuits 3 and 6, the counter circuit 7, the first memory circuit 4, etc. can respond at a sufficiently satisfactory speed even if a general digital I-C is used. Since it is not used, it has the advantage that the device configuration can be realized at a low cost. FIG. 5 is a block diagram showing one example of application of the present invention, in which the response signal shown in FIG. An example will be shown in which the time Tf required for falling to point B corresponding to the level of f) is measured.

In FIG. 5, reference numeral 101 denotes a pulse generator, and this pulse generator 101 outputs human input pulses PG and input clock pulses PGc of repetitive waveforms that are synchronized with each other at different levels. The above pulse generator 101
The input pulse PG outputted from the test device 10211C is supplied to a semiconductor device under test 10211C for a pulse response test. On the other hand, the input clock pulse P- output from the pulse generator 101
Gc is supplied to the peak value detection circuit 103. A trigram,
This peak value detection circuit 103 is similar to that shown in FIG. A response signal VO corresponding to the input pulse PG outputted from the semiconductor device under test 102 is supplied to the peak value detection circuit 103VC and is sent to the first and second comparators 105 and 106 via the buffer amplifier 104. supplied to The peak value detection circuit 103 detects the peak level Vp and outputs the first and second level setters 107,
108 VC is supplied to the A/D converter 109. The A/D converter 109 A/D converts the supplied peak level Vp and sends the digital signal to the terminal T.
It is output from lOl. The first and second level setters 107 and 108 each set a peak level Vp.
The level signal is arbitrarily set in the range of 0 to 100%,
The signal is supplied to the 71st and second comparators 105 and 106, respectively. The first and second comparators 105 and 106 respectively compare the two types of level signals and the response signal VO, and output a response signal V corresponding to the levels of the two types of level signals.
. detects the level point of and generates a detection timing signal. 110 is a gate circuit, and a clock pulse Cp is supplied to this gate circuit 110 from a clock pulse generator 111.

The gate circuit 110 connects the first and second comparators 10
A number of clock pulses Cp corresponding to the time interval between two level points are generated from the detection timing signal generated at 5,106.
Send out. The clock pulse Cp sent from the gate circuit 110 is counted by a counter circuit 112VC to detect the time interval between the two level points. The time interval detected by the counter circuit 112 is determined by the terminal T
It is supplied from lO2 to the external circuit, and the comparator circuit 11
3. A prescribed time interval is set in advance in this comparison circuit 113, and this time interval is compared with the time interval supplied from the counter circuit 112, and the comparison result is sent out from the terminal TlO3. Using the above configuration, first, the first level setter 107 is set to 90 (fl.
) and set the second level setter 108 to 0%.

Further, in the comparison circuit 113, a prescribed fall time TfO in the pulse response test is set. Next, when the circuit is operated, the first level setter 107 outputs a level signal of 90% of the peak level Vp output from the peak value detection circuit 103 to the first comparator 105. On the other hand, the second level setter 107 outputs a level signal of the peak level Vpf)0% to the second comparator 106VC. The first and second comparators 105 and 106 respectively compare the two types of level signals and the response signal VO to generate a response signal 0.
Two level setting points on VC are detected and the two detection timing signals are output to the gate circuit 110. The gate circuit 110 outputs a clock pulse Cp corresponding to the interval time between the two detection timing signals of the counter circuit 112VC1. The counter circuit 112 counts the clock pulses Cp to detect the time interval Tf between the two set points A and B of the response signal VO, and the comparator circuit 112
Outputs 3VC. The comparison circuit 113 compares the time interval Tf with the predetermined time interval TfO, and determines whether the semiconductor device under test 102
Various comparison results such as determination of quality and classification of the data are outputted from the terminal TlO3. The pulse response wave measurement method described above does not use any special circuits, so it can be constructed at low cost, and since it does not include analog elements such as sample-and-hold circuits, it can be used for high-speed repetitive input waveforms. In contrast, extremely good performance can be expected, and furthermore, measurement tests can be performed fully automatically.

This invention is not limited to the above embodiment,
For example, in the above embodiment, the case of measuring the fall time of the semiconductor device under test was explained, but this is not limited to measuring the fall time, and various other measurements such as the measurement of the rise time are possible. Needless to say. Further, in the above embodiments, a case has been described in which a semiconductor device is used as the circuit to be measured, but this is not limited to a semiconductor device, and it goes without saying that various circuit devices may be used. In addition, various modifications can be made to the present invention without departing from the gist thereof. As explained above, according to the present invention, the pulse response waveform output from the circuit under test and this pulse
: By detecting the peak value of the pulse response waveform by sequentially comparing n different reference levels output from the reference level generation circuit in synchronization with the response waveform using the level comparison circuit, It is possible to provide a pulse response waveform measurement method that allows pulse response measurement to be performed automatically with high accuracy and speed, and which allows the device configuration to be realized at a low cost.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a reference level generation circuit used in the above embodiment, and FIGS. A time chart for explanation and FIG. 5 is a block diagram showing an example of application of the above embodiment. 1,9,104...batshuaamp, 2...
...Level comparison circuit, 3,6...Gate circuit, 4,5...Memory circuit, 7,112...
・Counter circuit, 8...Reference level generation circuit,
10... Control circuit, 211-21.

Claims (1)

[Claims] 1. A level comparison circuit to which the pulse response waveform of the circuit under test is repeatedly input, and a reference level generation circuit that supplies n different reference levels to the level comparison circuit sequentially and in synchronization with the pulse input to the circuit under test. A method for measuring a pulse response waveform, comprising: a storage circuit for storing the comparison result of the level comparison circuit, and detecting a peak value of the pulse response waveform.