JPS59232496A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPS59232496A JPS59232496A JP10710083A JP10710083A JPS59232496A JP S59232496 A JPS59232496 A JP S59232496A JP 10710083 A JP10710083 A JP 10710083A JP 10710083 A JP10710083 A JP 10710083A JP S59232496 A JPS59232496 A JP S59232496A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- outer layer
- film thickness
- inner layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、印刷配線板の改良に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to improvements in printed wiring boards.
従来、印刷配線板例えば多層印刷配線板としては、第１
図に示すものが知られている。図中の１１＋１２は、夫
々絶縁板２，２表面に銅箔３．３を貼着した外層基板で
ある。この外層基板？＋＋１２間には、絶縁シート例え
ばデリゾレグ４・・・を介して内層パターン５・・・が
設けられている。また、こうした外層基板１１＋１２、
内層パターン５・・・及びデリゾレグ４・・・からなる
積層体の周囲には、無電解めっき、電気めっきによるめ
っき膜６が被膜されている。更に、同積層体には、スル
ーホール（図示せず）等が設けられている。Conventionally, as a printed wiring board, for example, a multilayer printed wiring board, the first
The one shown in the figure is known. Reference numerals 11 and 12 in the figure are outer layer substrates in which copper foils 3 and 3 are adhered to the surfaces of insulating plates 2 and 2, respectively. This outer layer board? An inner layer pattern 5 is provided between the ++12 and an insulating sheet such as a delisol leg 4. In addition, these outer layer substrates 11+12,
A plating film 6 formed by electroless plating or electroplating is coated around the laminate consisting of the inner layer patterns 5 and the delisol legs 4. Furthermore, the laminate is provided with through holes (not shown) and the like.
従来、前述した多層印刷配線板において、積層体の銅箔
３とめつき膜６の夫々の膜厚の和を非破壊式膜厚計によ
って測定するときは、例えば測定すべき箇所（Ａ点）の
めつき膜５に放射線をスポット状に照射し、その放射線
の散乱の状態により膜厚を求めていた。Conventionally, when measuring the sum of the respective film thicknesses of the copper foil 3 and the plating film 6 of the laminate using a non-destructive film thickness meter in the above-mentioned multilayer printed wiring board, for example, at the point to be measured (point A), The plating film 5 was irradiated with radiation in the form of spots, and the film thickness was determined based on the state of scattering of the radiation.
しかしながら、前述した構造の多層印刷配線板において
は、配線の高密度化のため内層・母ターフ５・・・が段
違いに高集積化し、互いに近接しているため、平面的に
見た場合はとんど余分なスペースが存在しない。したが
って、膜厚を測定すべき箇所（Ａ点）の下に位置する積
層体には、内層パターン５が存在する。その結果、測定
時、Ａ点に照射された放射線がＡ点の下に位置する内層
・ぐターン５により干渉され、膜厚を正確に測定するこ
とができない。However, in the multilayer printed wiring board with the above-described structure, the inner layer/mother turf 5... is highly integrated at different levels due to the high wiring density and is close to each other, so when viewed two-dimensionally, the inner layer/mother turf 5... There is no extra space. Therefore, the inner layer pattern 5 exists in the laminate located below the location where the film thickness is to be measured (point A). As a result, during measurement, the radiation irradiated to point A is interfered with by the inner layer groove 5 located below point A, making it impossible to accurately measure the film thickness.
本発明は上記事情に鋭みてなされたもので、表向の導体
の膜厚を干渉されることなく、正確に測定できる印刷配
線板を提供することを目的とするものである１、
〔発明の概要〕
本発明は、外層基板間の一部に絶縁シートのみからなる
領域を設けることによって、前記領域の」−（又は下）
の表面の導体の膜厚を正確に測定できることを骨子とす
る。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a printed wiring board in which the film thickness of the surface conductor can be accurately measured without interference. Summary] The present invention provides a region consisting only of an insulating sheet in a part between the outer layer substrates, thereby making it possible to
The main point is to be able to accurately measure the film thickness of the conductor on the surface of the
以下、本発明の一実施例に係る多層印刷配線板を第２図
及び２４”、 ３図を参照して説明する。Hereinafter, a multilayer printed wiring board according to an embodiment of the present invention will be described with reference to FIG. 2 and FIGS. 24'' and 3.
図中の１１はワーク板である。このワーク板１１の中央
部には、製品加工領域１２が設けられている。前記ワー
ク板Ｊ１の３つのコーナーには、テストクー、Ｊｑン１
３・・・が設けられる。同ワーク板１１には、該ワーク
板１ノを所定のテーブル等に位置合わせするだめのツー
リングホール１４・・・が、前記テストクーポン１３・
・・に近接して設けられている。寸だ、前記ワーク板１
１の両面は、夫々絶縁板１５．１５表面に銅箔１６゜１
６を貼着した外層基板１７．．１７．となっている。こ
れら外層基板１７．．１７．間には、絶縁シートとして
のプリプレグ１８・・・を介して導電体としての内層・
ぐターン１９・・・が設けられている。こうした外層基
板１７１ ＋１７ｔｓ内層・ぐターン１９・・・及びプ
リプレグ１８・・・等からなる積層体には、内層・？タ
ーン１９・・・が全く存在しないプリプレグ１８・・・
のみからなる領域２０・・・が設けられている。これら
領域２０・・・は前記テストクーポン１３・・・、ツー
リングホール１４・・・に夫々近接している。前記積層
体の周囲には、無電解めっき、電気めっきによるめっき
膜２１が被覆されている。11 in the figure is a work plate. A product processing area 12 is provided in the center of the work plate 11 . At the three corners of the work plate J1, there are test plates and Jqn1.
3... is provided. The work plate 11 has tooling holes 14 for positioning the work plate 1 on a predetermined table or the like.
It is located close to... That's it, the work plate 1
Both sides of 1 are covered with copper foil 16°1 on the surface of the insulating plate 15 and 15, respectively.
6 is attached to the outer layer substrate 17. ．． 17. It becomes. These outer layer substrates 17. ．． 17. In between, there is an inner layer as a conductor via a prepreg 18 as an insulating sheet.
Turn 19... is provided. The laminate consisting of such an outer layer substrate 171 +17ts inner layer 19... and prepreg 18... etc. has an inner layer ? Prepreg 18... where turn 19... does not exist at all.
A region 20 . . . consisting only of These regions 20 are close to the test coupons 13 and tooling holes 14, respectively. The periphery of the laminate is coated with a plating film 21 formed by electroless plating or electroplating.
しかして、本発明によれば、外層基板１７．。According to the present invention, the outer layer substrate 17. .
１７□間の一部にプリプレグ１８・・・のみからなる領
域２０・・・が設けられているため、この領域２０・・
・上（又は下）に位置する銅箔１６及びめっき膜２１
寵）Ｊ非破廉式膜厚計により正確に測定できる。Since a region 20... consisting only of prepreg 18... is provided in a part between 17□, this region 20...
- Copper foil 16 and plating film 21 located above (or below)
Can be measured accurately using a non-destructive film thickness meter.
また、前記領域２０・・・は、夫々前記テストクーポン
１３・・・、ツーリングホール１４・・・に夫々近接す
るように設けられているだめ、領域２０・・・を目視で
きないにもかかわらず、容易にその位置を確認できる。Furthermore, since the regions 20 are provided close to the test coupons 13 and the touring holes 14, respectively, although the regions 20 cannot be visually observed, Its position can be easily confirmed.
なお、本発明に係る印刷配ね板としては、上記実施例の
ものに限らない。例えば、第４図に示す如く、ワーク板
１１内に２個の製品加工領域２１．２１を設け、この製
品加工領域２１゜２１で狭址れ／ξ部分に対応する積層
体にプリプレグＩ８・・・のみからなる領域２２を設け
た構造の多層印刷配線板でもよい。址だ、第５図に示す
如く、めつき膜、銅箔を・ぐターニングしてめっキ膜・
ぐワーク２１′、銅箔パターン１６′カラする配線パタ
ーン２３を形成した構造の多層印刷配線板でもよい。第
５図図示の多層印刷配線板によれば、配線パターン２３
が一目でわかるため、膜厚の測定位置の確認が上記実施
例より一層簡単である。更に、第６図に示す如く、積層
体に導電体としての金属シート２４を積層し、かつこの
金属シート２４の膜厚を測定すべき位置に対応する部分
ケ開口した＋１４造の印刷配線板でもよい。Note that the printed layout board according to the present invention is not limited to those of the above embodiments. For example, as shown in FIG. 4, two product processing areas 21.21 are provided in the work plate 11, and prepreg I8... A multilayer printed wiring board may have a structure in which a region 22 consisting of only . Then, as shown in Figure 5, turn the plating film and copper foil to form the plating film.
A multilayer printed wiring board having a structure in which a working piece 21' and a wiring pattern 23 colored with a copper foil pattern 16' are formed may also be used. According to the multilayer printed wiring board shown in FIG.
Since this can be seen at a glance, confirmation of the film thickness measurement position is easier than in the above embodiment. Furthermore, as shown in FIG. 6, a printed wiring board of +14 construction may be used, in which a metal sheet 24 as a conductor is laminated on a laminate, and a portion of the metal sheet 24 corresponding to the position where the film thickness is to be measured is opened. good.
以上詳述した如く本発明によれば、表面の導体の膜厚を
正確に測定できる印刷配線板を提供できるものである。As described in detail above, according to the present invention, it is possible to provide a printed wiring board on which the film thickness of the surface conductor can be accurately measured.
第１図は従来の多層印刷配線板の断面図、第２図は本発
明の一実施例に係る多層印刷板の平面図、第３図は第２
図のＸ−Ｘ線に沿う拡大断面図、第４図〜第６図シ」、
本発明の他の実施例に係る多層印刷配線板の説明図であ
る。
１１・・・ワーク板、１２．２１・・・製品加工領域、
１３・・・テストクーポン、１４・・・ツーリングホー
ル、１５・・・絶縁板、１６・・・銅箔、１６′・・・
銅箔パターン、１７．．１７．・・・外層基板、１８・
・・デＩＪ ｆレグ（絶縁シート）、１９・・・内層ｉ
Ｅターン（導電体）、２０ 、２．２・・・プリプレグ
のみからなる領域、２ノ・・・めっき膜、２１′・・・
めっき膜・ぞターン、２３・・・配線ツクターン、２４
・・・金属シート（導電体）。
出願人代理人 弁■！± 鈴 江 武 彦第１図
第２図
第３図FIG. 1 is a cross-sectional view of a conventional multilayer printed wiring board, FIG. 2 is a plan view of a multilayer printed wiring board according to an embodiment of the present invention, and FIG.
Enlarged sectional view taken along the line X-X in the figure, Figures 4 to 6
FIG. 7 is an explanatory diagram of a multilayer printed wiring board according to another embodiment of the present invention. 11... Work plate, 12.21... Product processing area,
13...Test coupon, 14...Touring hole, 15...Insulating plate, 16...Copper foil, 16'...
Copper foil pattern, 17. ．． 17. ...Outer layer substrate, 18.
...De IJ f leg (insulating sheet), 19...inner layer i
E-turn (conductor), 20, 2.2... region consisting only of prepreg, 2no... plating film, 21'...
Plating film/Zo-turn, 23...Wiring Tsuk-turn, 24
...Metal sheet (conductor). Applicant's agent Ben■! ± Takehiko Suzue Figure 1 Figure 2 Figure 3
Claims (1)
して設けられた導電体とを具備する印刷配線板において
、前記外層基板間の一部に絶縁シートのみからなる領域
を設けたことを特徴とする印刷配線板。A printed wiring board comprising two outer layer substrates and a conductor provided between these outer layer substrates with an insulating sheet interposed therebetween, characterized in that a region consisting only of the insulating sheet is provided in a part between the outer layer substrates. Printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10710083A JPS59232496A (en) | 1983-06-15 | 1983-06-15 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10710083A JPS59232496A (en) | 1983-06-15 | 1983-06-15 | Printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59232496A true JPS59232496A (en) | 1984-12-27 |
Family
ID=14450457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10710083A Pending JPS59232496A (en) | 1983-06-15 | 1983-06-15 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59232496A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0314285A (en) * | 1989-06-13 | 1991-01-22 | Yamazaki Kogyo Kk | Manufacture of printed wiring board |
-
1983
- 1983-06-15 JP JP10710083A patent/JPS59232496A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0314285A (en) * | 1989-06-13 | 1991-01-22 | Yamazaki Kogyo Kk | Manufacture of printed wiring board |
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