JPS59232439A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an element separating region with a fine width by a method wherein a U-shape groove is formed in a semiconductor substrate piercing through an insulating film and a semiconductor layer is made grow on the inside surface of the groove and an impurity is diffused into the semiconductor layer. CONSTITUTION:After an SiO2 film is formed on the surface of a P<-> type silicon substrate 1, a U-shape groove 5 is formed piercing through the SiO2 film by an unisotropic etching. A P type impurity is ion-implanted into the inside surface of the U-shape groove 5 using the SiO2 film as a mask and the substrate is subjected to a heat-treatment. After an SiO2 film formed inside the groove by a thermal oxidization is removed, a non-doped epitaxial Si layer 8 is made grow on the inside surface of the groove and at the same time the impurity is diffused into the epitaxial layer 8 from the impurity implanted region of the inside surface of the groove. An SiO2 film 9 is formed on the surface of the epitaxial layer 8 and an element separating region is formed.

Description

Detailed Description of the Invention (af) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolation region between elements.

(b) Prior Art and Problems The isolation regions between elements in semiconductor ICs with a relatively high IC are conventionally often formed using the 44th oxidation technology (LOCO8 method) or the U-groove isolation technology. Ta.

Selective oxidation technology selectively thermally oxidizes the surface of a semiconductor substrate using an oxidation-resistant film patterned to a predetermined size corresponding to the element formation region as a mask, and separates and defines the terminal formation region on the semiconductor substrate surface. This is a technology to form an isolation oxide film.

However, in this technology, the bird's beak BB of tW (D width (=) extends below the oxidation-resistant film SiN to an extent comparable to J: the thickness of the selective oxide film OX1), which is not shown in FIG. Therefore, the width of the separation region becomes wider (the minimum width of the separation region is about 2.2 [μml]), which hinders the high density of the IC, and the width of the bird's beak is determined by the manufacturing conditions. Therefore, it is difficult to keep the area of the element formation region defined by the 5ζ selective oxide film constant. In semiconductor memory devices, etc., there has been a problem in that device performance deteriorates due to variations in the amount of gaffer capacitor valleys due to variations in capacitor area when these devices are integrated at high density. A U-shaped separation groove is formed on the substrate surface using anisotropic etching technology, and the U-shaped portion KiI
an insulator thick enough to fill the lip on the substrate;
A U-shape in which an insulator or polycrystalline silicon is flatly embedded by forming a fake or high resistivity polycrystalline silicon layer and uniformly etching and removing the insulating layer or polycrystalline silicon layer from the top surface. Separation r; +p is formed, and the U-shaped portion ~
This is a technique for defining element formation i pruning branches 11i1 by ill rjQ.

However, there are problems with the U u'r' separation technique (bow 1, the method of plane etching the above insulating layer or polycrystalline glue 7M is extremely complicated and unsuitable for the manufacturing process, and the U-shaped part i1i Since the formation of the insulating layer to completely fill the groove is done by the plasma coating method which has good coverage, the leakage current increases on the surface of the element formation area due to the plastic layer's adhesiveness, and the gear carrier's generation time is reduced. (c) Purpose of the Invention The present invention provides a method for determining the size of semiconductor substrates by using phosphorography technology to precisely define the dimensions of semiconductor substrates. This paper provides a method for forming a 1IIIL chain acid with an element weight without impairing crystal quality.
The purpose is to improve the quality and increase the density of high-density, high-density 4-U.

(d) Structure of the invention, that is, the present invention is a half-column 17I; In a method for manufacturing a device, when an element j'+8'' is formed in a region ti11 on a semiconductor substrate surface, an insulating film is formed on the semiconductor substrate surface. , forming a U-shaped groove in the semiconductor substrate through the insulating film, selectively implanting impurity ions into the inner surface of the U-shaped groove, and forming the groove in the U-shaped groove.
The present invention is characterized by comprising a step of selectively epitaxially growing a semiconductor layer on the inner surface of the shape recess, simultaneously diffusing the implanted impurity into the semiconductor epitaxial layer, and oxidizing the surface of the semiconductor epitaxial layer.

(e) Embodiments of the Invention The present invention will now be explained in detail with reference to the drawings.

Figures 2 (A) to (F) and Figures 3 (A) to (E) are process cross-sectional views of one embodiment, and Figure 4 (I) to (E) are process cross-sectional views of one embodiment.
FIG.

Refer to FIG. 2(A). When forming, for example, a MO8IC using the method of the invention, for example, 2000 [:A
) is formed, and then an opening 3 of, for example, 1 μm (11 J) is formed to define the width of the isolation region (Iso) on the substrate.
A resist film 1 is formed, and then the resist film 4 is formed.
Using an anisotropic etching method that is dominant in the direction perpendicular to the substrate surface, such as an active 1-on etching method, the 5i02 film 2 is penetrated onto the 1st surface of the St substrate.
[μmp) 0 with 41j, l, degree of laziness d)
A glyph-shaped groove 5 is formed. In addition, the etching gas in the above reactive ion etching method is usually 5 in.
For Si, use carbon tetrafluoride (Cj(4), etc.) for x1 shift. The U-shaped groove 5 is filled with a p-type impurity, i.e., a dfll element (B) at a dose of 3X 10" [:atm/ci:] and an acceleration energy of about 70 to 100 (KeV), using the 5I02 film 2 as a mask. Ions are selectively implanted into the inner surface (especially the bottom surface) at a high concentration.

6 indicates the B+ implantation region.

Refer to FIG. 2(c) Next, after removing the resist film 4, a thermal oxidation treatment is performed at a temperature of about 1050 [°C:], and a second 5i02J with a thickness of about 2000 mm is formed on the inner surface of the 0-shaped groove 5. (This removal process increases the thickness of the SiO2 film 7), and then the entire surface is etched by a normal wet etching method until the SiO□ film on the inner surface of the U-shaped surface 5 is removed. At this time, the thickness of S ] 02 MM 2 on the upper surface of the substrate 1 returns to almost the original thickness. This process removes the crystal defects formed on the inner surface of the O-shaped groove 5 during the reactive ion etching and ion implantation, and also removes the B+ on the inner surface of the U-shaped groove 5.
This was added just in case to increase the roughness of the surface, and normally it can be omitted.

This is because the crystal defects are sufficiently removed in the next epitaxial growth process, and the B+
This is because autodoping of B+ to the Evita quince layer, which will be described later, can be carried out sufficiently without particularly increasing the surface variation.

Referring to Figure 2), the reaction mixture was then treated with trichlorosilane (S 1 Hcls).
), using a conventional 81 selective epitaxial growth technique carried out in the reaction gas of about 0.1 Torr at a temperature of about 1000 ('C), to form a U-shaped front surface in which Si is optically used. For example, a thickness of 3 is selectively applied to the inner surface of 5.
Non-doped St of about 000 [A] is grown. At this time, B+ is diffused (autodoped) into the Si epitaxial layer from the B+ implanted region 6 formed on the inner surface layer of the U-shaped groove 5, and the Si epitaxial layer becomes p+ type St.
Evitakinyarukō 8. The epitaxial layer 8 may be formed to a thickness that fills the 0-shaped groove 5 with the upper surface of the 0-shaped groove 5. See FIG. For example, 2000[:A
] A third 5in2 film 9 having a thickness of about 100 psi is formed to complete the inter-element isolation region (Iso) according to the present invention. At this time, the 5in2 film 2 on the element formation region (Dev) has a thickness of 3000~
The thickness becomes about 4000 (A).

Refer to FIG. 2(f). Next, after selectively removing 5IO22 on the element formation region (Dev), a gate oxide film 10 is formed on the element formation region (Dev) according to a normal MOS transistor formation method. A polycrystalline silicon layer is formed on the substrate, a polycrystalline silicon gate electrode 11 is formed by buttering, and then selective ion implantation of n-type impurities is performed using the gate electrode 11 as a mask. Te n++ sauce,
Drain region 12a.

12b is formed.

Thereafter, the formation of an insulating film (not shown), the formation of electrode contact windows, the formation of wiring, etc. are performed to complete the MO8IC.

Refer to FIG. 3(a) When forming, for example, a bipolar IC using the method of the present invention, as usual, for example, n+
+A buried diffusion region 13 is formed on the substrate, e.g.
A substrate to be processed for forming a bipolar IC on which an 11-type St.
[λ] forming a 5in2 [2] of SiO2
IS of a width corresponding to the element isolation region (Iso) width is formed on the film 2.
1-1 Forming a resist film 4 to fill the holes 3. 1-1 Using the resist film 4 as a mask, apply the same active ion etching method as in the previous embodiment to form a resist film 4 on the surface of the substrate to be processed so that the bottom part is p-. A 0-shaped groove 5 reaching into the type Si substrate 1 is formed.

Figure 3 (b)
:42 as a mask, B+ ion implantation was performed, and the U
After removing the resist 1144 as shown in FIG. The U in the groove 5
A Si epitaxial layer is selectively grown that fills the shape groove 5 almost with the upper surface cut out. At this time, as described above, auto-doping of B+ from the high concentration B+ implantation region 6 is performed on the Evita core layer, and the layer becomes p+ type St epitaxial/Fi8. Note that before the selective epitaxial growth of S1, a process of removing crystal defects on the inner surface of the U-shaped groove as explained in the previous *L embodiment may be added.

Referring to FIG. 3), the p+ type Sj in the 0-shaped groove 5 is then removed by a normal thermal oxidation method.
For example, 200 (IC:A
forming a third S i O2M 9 with a thickness of about :];
The inter-element isolation region (Iso) is completed. The separation in this case is mainly junction separation.

Referring to FIG. 3(E), the device formation region (Dev) is then
p-type base region 15. n++ emitter region 16. n+
+Collector contact region 17 is formed.

Although not shown, the bipolar IC is completed without any conceptual formation, insulating film formation, etc.

In both cases, a 5in2 film was used as a protection film on the substrate surface when forming a U-shaped separation groove, but a nitride Norikono (Si3NJ) film was used as the Ek protection film.
IIC,! may also be used.

This is 5i021. on the element isolation region. I! J is formed particularly thick 7, and the distribution bar 1 tracing over the separation region is separated, I
li (, 81 in the i), improves the resistance, reduces the stray 6M of the wiring, and as in the bipolar IC (as in the case of offshore isolation structure). This is useful for reducing capacitance.The method for forming 11 regions between elements when using a 5iaN4 film for the above surface 1.↓ protective film will be explained with reference to FIG. .

Refer to FIG. 4(a). For example, on p-type S1 group, 50%
0 to 10 (an initial HVH plated film 18 with a thickness of about 10 LA'3 is formed, and a Si 3N4 film 19 with a thickness of about 1000 CA') is formed on the initial thickened gap 18 by a normal chemical vapor deposition method. , an opening 3 having a width corresponding to the width of the inter-element isolation region (Iso) is formed on the Si3N film 19 using a normal photo process.
Form a resist film 4 having a 5isN4 film 19 and an initial oxide film 1 by reactive ion etching
8 and form a U-shaped casting 5 on the substrate surface.

Refer to FIG. 4(b) Next, the remaining film of the resist sample 4 and the Si3N4 film 1
9 Perform ion implantation using the initial oxide film 18 as a mask, and implant B+ ions at a high concentration into the inner surface (especially the bottom surface) of the U-shaped groove 5. After removing the reference resist film 4, the U-shaped r'l'?5
By selectively growing a Si vitreous layer within the 0
A p+ type St-type hard layer 8 is formed in the shaped groove 5. (As described above, autodoping from the B+ implanted region 6 results in a SIL+ type.) Refer to Figure 2144) Then, using the Si3N film 19 as a mask, a suitable selective oxidation method is applied to the upper surface of the p+ type SJ layer deposit 8. For example, the third S of 3000 (A) IH degree
102i1@9 is formed to form the inter-element isolation region (
Furthermore, during the selective oxidation, a bird's beak extends from the third SiO2 film 9;
The thickness of 5i02i1-9 is the conventional oxide film structure (
(see FIG. 1), the extension width of the bird's beak is minute.

Thereafter, Si, N, and films 19.
After removing the initial oxidation 115j i s, semi-solid elements are formed in the region in a conventional manner.

(f) Effects of the Invention As is clear from the above embodiments, the width of the element isolation region is determined by the method of the present invention when forming the U-shaped portion t4ir.

It is possible to create an inter-element isolation region with a width of one inch, which is the limit of silver (currently about 1 [μm]) that can be patterned using photolithographic technology. It can be formed with high precision without variation, and as a result, the unevenness of the ingrowth in the element formation region is also extremely reduced.

Therefore, according to the present invention, it becomes possible to further integrate the semiconductor heavy-duty C at a higher density and to improve its quality.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the technique for determining the element amount P″1 by the conventional selective oxidation method, and FIG. 2 (A) to (F) and FIG. 4(a) to 4) are process sectional views of different embodiments of the isolation region forming method, and FIGS. 2 and 9 are silicon dioxide membranes, 3-holes, 4-resist membranes, 5i: U-shaped a
4.6 li surface element implantation S54 area, 8 li I)”
Type/l) Con-Evita Kinyal layer, 18 is initial oxidation Jl
iJ, 19c silicon nitride film, ISO'l'2n:
``The separation area between children, Dcv indicates the area where the elements are formed. Agent Patent Attorney Hiroshi Matsuoka Seibu 1 ``Mine f Example Mine 2 Note ¥-2 Old Close JIP 4 Otori

Claims (1)

[Claims] When forming an isolation region between elements on the semiconductor substrate surface, an insulating film is formed on the semiconductor substrate, a U-shaped groove is formed in the semiconductor substrate surface passing through the insulating rainbow, and a U-shaped groove is formed on the inner surface of the (1-shaped groove). selectively implanting impurity ions, selectively epitaxially growing a semiconductor layer on the inner surface of the U-shaped groove, and simultaneously diffusing the implanted impurity into the semiconductor epitaxial layer; A manufacturing method for a semi-heroic outfit +4, which is characterized by a technique that turns the front into a milky one, and has Vt.