JPS59230419A - Variation amount detecting and relaying device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a change detection relay device that detects a failure occurring in a power system based on a change in the amount of electricity.

[Technical background of the invention and its problems]

In some power systems, in order to detect system failures, a change width detection current relay (hereinafter referred to as ΔI IJ relay) that detects the change width of the amount of electricity is installed instead of an overcurrent relay.
Depending on the detection result of this ΔI relay, various judgments may be made.

The reason for this is that, for example, the difference in magnitude between a large power current flowing through the grid and the fault current when a ground fault or short circuit fault occurs in the grid is extremely small, and the system responds only to the magnitude of the current. This is because even if an overcurrent relay is used, it may not be possible to distinguish whether this large current is due to a failure or not.

As mentioned above, the ΔI relay operates when the current changes, so when using it in a device that issues a trip command to the circuit breaker after a certain period of time after a system failure occurs, use the ΔI relay. It is necessary to somehow extend the operational output of .

This stretching method will be explained. In Figure 1,
Output 21j of ΔERICE 1: Input to on-delay timer 4 via F1 circuit 3. The output of the on-delay timer 4 is inverted by the NOT circuit 5 to obtain an output 6. The operation is as shown in the time chart in Figure 2, and the output 6 after stretching is △■ The output 2 of the relay l is
It is obtained by stretching 1 and 17 times. In addition, in Figure 1,
An on-delay timer 4 is used as a timer for stretching, and knot circuits 3 and 5 are connected before and after it.
Although the off-delay timer has been described as an overall function, the off-delay timer is usually constituted by the off-delay timer 4 when focusing on its time limit.

In particular, the repeated 5W of △l relay l as shown in Figure 3
For 11 crops, the last output that is output within the extension time Tl (in Figure 3, the second output crab is output within the extension time Tl)
, if it is necessary to extend the time by , use an off-delay timer 4 and connect knot circuits 3 and 5 before and after it.
An off-delay timer is often used as the overall function.

In such a circuit configuration, when focusing on the timer input, when there is no failure in the system and the ΔI relay output 2 has a logical value "0", the timer input has a logical value rlJ. but,
When the on-delay timer 40 control power is turned on or momentarily cut off, the timer output rises from "0" to rlJ.

Even though the relay output 2 is "0", the timer input changes from rOJ to rlJ, so the output 6 changes from rlJ to "0", and the same output as when a failure occurs in the grid is generated. Such unnecessary output may cause the circuit breaker to be tripped incorrectly.

As a countermeasure to this problem, a device as shown in FIG. 4 has been considered. In FIG. 4, the output 8 of the control power supply abnormality detection circuit 7 becomes "1" when the power supply is normal, and becomes "0" when an abnormality is detected. This output 8 is input to an AND circuit 11 via an on-delay timer 9 having a time limit T2e. The other input of the AND circuit 11 has ΔI relay output 2.
The output 6 after stretching is connected. Note that the time limit TI of the on-delay timer 40 and the time limit T2 of the off-delay timer 9 are set so that Tl<Tt. The operation of such a device when the power supply is interrupted will be explained with reference to the time chart shown in FIG. During the period when the control power level drops below the abnormality detection level,
The output 8 of the power supply abnormality detection circuit 7 is "0". Then, the output lO of the on-delay timer 9 @1 is the period in which the output 8 of the source failure detection circuit 7 is "0" and "0"
Tz time period II'i after changing from to rlJ remains at "0". On the other hand, even if there is no fault in the grid and the △I relay output 2 remains "0", the level of the on-delay timer 40 control power supply has decreased, so the output of the on-delay timer 4 becomes rOJ, and the power supply returns to normal. After that, time limit T
It becomes rlJ with a delay of I. In other words, the apparent behavior is the same as if a failure had occurred in the grid. Here, the output 6 after being extended by the on-delay timer 4 is rlJ until the time period T1 elapses after the power is restored to normal.
However, while the output IO of the on-delay tie T9 continues to be "0" in the AND circuit 11, the output 6 after stretching becomes rOJ. Therefore, the final output 12 is “0
"t"!F, and unnecessary outputs are prevented from being generated.A similar operation occurs when the power is turned on, so that no unnecessary outputs are generated at output 12.In this way, as shown in Fig. 4, The device can prevent unnecessary output when the power is turned on or momentarily interrupted.

However, if the time period T1 is long, the above-mentioned Tl<T.

Because of the need to satisfy the relationship, the locking time due to time limit T2 must be made longer, and depending on the system conditions immediately after the power is turned on or a momentary power outage, it may become locked even when it should be operating, and the original function of the ΔI relay 1 may be interrupted. ′ was severely limited.

[Purpose of the invention]

The present invention has been made in order to eliminate the above-mentioned drawbacks, and it prevents malfunctions caused by turning on the control power or momentary power outage, etc., and also improves the reliability of responding to system failures even immediately after turning on, momentary power outage, etc. High change detection level 1! The purpose is to provide equipment.

[Summary of the invention]

In order to achieve the above object, the present invention uses a relay to detect a change in the amount of electricity in a spot power system, a power supply abnormality detection circuit to detect whether the control power supply voltage is below a predetermined level, and operates the relay. The output of time is used as the set input of the memory circuit,
Further, the on-delay timer is activated upon completion of the operation of the relay, and the storage circuit is reset when the on-delay timer 2 times up or when the control power supply voltage falls below a predetermined level.

[Embodiments of the invention]

An embodiment of the present invention will be described with reference to FIGS. 6 and 7.

In FIG. 6, ■ is a ΔI relay as a relay that responds to changes in the amount of electricity in the power system. 2 is the △I relay output, and the memory circuit (hereinafter referred to as flip-flop) 1
It is input to the set input terminal of No.3. 14 is a knot circuit, which inverts the ΔErelay output 2. 15 is an AND circuit which inputs the output of the NOT circuit 14 and the Q terminal output 16 of the flip-flop 13 and outputs its logical value. 4 is an on-delay timer, which delays the output of the AND circuit 15 by a time limit Tl. Reference numeral 7 denotes a power supply abnormality detection circuit, which normally outputs a logical value rlJ, and outputs all "0" when the control power supply voltage falls below the abnormality detection level. 8 is the output of the power supply abnormality detection circuit 7. 19 is a NOT circuit, which inverts the power supply abnormality detection circuit output 8; 20 is an OR circuit which inputs the output of the NOT circuit 19 and the output of the on-delay timer 4, and applies the logical sum thereof as an output 21 to the reset input terminal of the flip-flop 13.

17 is an AND circuit which inputs the Q terminal output 16 of the flip-flop 13 and the power supply abnormality detection circuit output 8, and outputs it as a trip command 18 of the logical private money breaker.
Next, the operation of this embodiment will be explained with reference to FIG.

As shown in FIG. 7(a), if a failure occurs in the system and the current changes repeatedly within the extension time Tl when the control power supply is normal, the first I relay l
Due to the operation, △I relay output 2 becomes "1", flip-flop 13 is set, and its output 16 becomes
becomes. Next, when △Erelay output 2 becomes “0”,
Both inputs of the AND circuit 15 become "1" and the output is r
lJ, and the on-delay timer 4 starts counting. However, before time-up (time limit T1 elapses), △I relay output 2 becomes "1" due to the operation of △eliciy 1 for the second time, and the AND condition of AND circuit 15 no longer holds true, causing the on-delay timer to count 4. Abort. By making this on-delay timer 4, which is able to return to the initial state from the state where it was counting halfway within the pulse width of the △ relay output 2, the second △■
After the relay output becomes rOJ, the output becomes rlJ after the time limit Tl has elapsed. At this time, the output of the NOT circuit 19 is rQJ, but the output of the on-delay timer 4 is rl.
J, the output 21 of the OR circuit 20 becomes "1".
Therefore, the flip-flop 13 is reset. Therefore, the output 18 of the AND circuit 17 changes from "1" to "0" and is output as a trip command.

Next, as shown in Fig. 7 Φ), when the control power supply is momentarily cut off, when the control power supply voltage becomes below the abnormality detection level, the power supply abnormality detection circuit output 8 becomes "0", and the OR circuit 2
The output 21 of 0 becomes "1" and the flip-flop 13 is reset. Since the flip-flop 13 is reset and its output 16 becomes "0", the AND circuit 15
The AND condition is not satisfied, and the on-delay timer 4 is not activated.

-t, that is, the trip command 18 is not output either. Further, if the control power supply voltage exceeds the abnormality detection level and a failure occurs in the system after the control power supply is restored, a trip command 18 is output by the operation shown in FIG. 7(a).

Similarly, no trip command is output when the control power is turned on.

Therefore, in the conventional device shown in FIG. 4, when the control power is momentarily cut off and then turned on, the time limit is T, and the longer time limit is T.

However, in this embodiment, the trip command 18t was not output only during the period when the control power supply voltage was below the abnormality detection level, and a system fault occurred immediately after the momentary power cut and power on. In this case, trip command 1
8't- can be output.

According to this embodiment, the trip command 18 is not outputted by mistake due to momentary power interruption or turning on of the control power, and
Even when a system failure occurs immediately after the power is turned on, the trip command 18 can be output to trip the breaker.

In Fig. 6, when the control power supply is turned off and on,
When the output 8 of the power supply abnormality detection circuit 7 becomes "0", the output 16 of the flip-flop 13 is locked, and this is a reset signal for the flip-flop 13 when the control power supply falls or rises. When the output of the OR circuit 21 and the flip-flop 13 themselves are not coordinated, a trip command is not issued even if the output 16 becomes "1" transiently. Therefore, there is no need to use flip-flops.

Next, another embodiment of the present invention will be described with reference to FIG.

In FIG. 8, 221. j. This is an on-delay timer, and provides an output 23 obtained by delaying the power supply abnormality detection circuit output 8 by a time period T3 to the NOT circuit 9 and the AND circuit 17.

When the control power supply changes from an abnormal state to a normal state, the power supply abnormality detection circuit output 8 changes from "0" to "1", but the output 23 of the on-delay timer 22 changes to "0" with a delay of time T3.
From rlJ and gal. Since the flip-flop 13 continues to be reset for this delay time, the output 16 of the flip-flop 13 remains at "0".

Therefore, according to this embodiment, even if the ΔEllisor 1 itself temporarily generates an erroneous output even after the control power source has been brought up to a normal state, the trip command 18 will not be erroneously output. . Moreover, since this time limit T3 may be a period in which an erroneous output of ΔI'IJ ray 1 occurs, the time limit T3 of the conventional device is sufficient. A much shorter time period is better.

In the above explanation, the relay that responds to changes in the amount of electricity is a change width detection current relay (△IIJ relay), but relays that respond to changes in other detection targets such as voltage, power, frequency, etc. can also be used. It's okay.

〔Effect of the invention〕

According to the present invention, as explained above, turning on the control power,
It is possible to provide a highly reliable change detection relay device that can prevent malfunctions due to instantaneous power outages, etc., and can respond to system failures even immediately after power-on, instantaneous power outages, etc.

[Brief explanation of drawings]

Figure 1 is a configuration diagram showing an example of a conventional device, Figures 2 and 3
The figure is a time chart showing the operation of the device shown in FIG. 1, FIG. 4 is a configuration diagram showing another example of the conventional device, and FIG.
6 is a block diagram showing an embodiment of the present invention, FIG. 7 is a time chart showing the operation of the device shown in FIG. 6, and FIG. 8 is a time chart showing the operation of the device shown in FIG. It is a block diagram which shows another Example of this invention. 1... Relay (△I relay) 4... On delay timer 7... Power supply abnormality detection circuit 13... Flip-flop 15... AND circuit 20... OR circuit (
7317) Agent Patent Attorney Noriyuki Chika (
tl or 1 person) Fig. 1 Otsu Eri Relay Upper Blade 2'', Knee - Fig. 3 Fig. 4 Fig. 5 It - 11 - d bi 1 Ekorou ;: 1 = 1,〃 2 1 ・0゜11, Onten 14F4F4L -m-O+ Da/J Anzu 1yo'υOh Boka 6:'・--11-1

Claims (1)

[Claims] A relay that responds to changes in the amount of electricity in the power system, a power supply abnormality detection circuit that detects whether the control power supply voltage is below a predetermined level, and a memory circuit that inputs the output of the relay and is set during its operation. an AND circuit that inputs a signal obtained by inverting the output of the relay and the output of the memory circuit and outputs the entire logical product; a timer that outputs the output of the AND circuit with a set time delay; A change amount detection repeater comprising an OR circuit which takes as inputs a signal obtained by inverting the output of the detection circuit and the output of the ←≠1000+→ timer and gives the logical sum thereof as a reset signal for the storage circuit. Electrical equipment.