JPS58154013A - Monitor circuit - Google Patents

Abstract

PURPOSE:To prevent malfunctions of a monitor circuit, by detecting that either one of plural input signals continues longer than a fixed time to store it in a corresponding memory circuit and inhibiting the input of the corresponding input signal with the output of the memory circuit. CONSTITUTION:For instance, a relay circuit Si among those circuits S1-Sn has a malfunction and delivers signals continuously. In such a case, an inhibiting circuit 5-i opens a gate in its initial state. Then an OR circuit 1 has an output of H, and a timer 2 has an output of H when the set time elapses. At the same time, an AND circuit 3-i also has an output of H and a storage circuit 4-i maintains an output of H. The circuit 5-i closes the gate to inhibit the input of a signal Si to the timer circuit 2 at a moment when the memory 4-i delivers a level H. This can prevent a mistake that is caused when another relay has a normal operation while either one of the relay circuits has a fault. Furthermore the faulty relay Si is detected by an output Ki of the memory 4-i.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monitoring circuit that constantly monitors equipment as a method for improving the reliability of control equipment and the like.

For convenience of explanation, the present invention will be explained using a monitoring circuit provided in a protective relay (hereinafter simply referred to as a relay) as an example.

Generally, protection circuits and devices in electric power systems are constantly monitored by a monitoring circuit to check whether they are malfunctioning or not.

A conventional monitoring circuit for this type of protective relay is shown in FIG. In the figure, (l) is an OR circuit, (2
) is a time-limited instantaneous recovery timer circuit with operating time T1, ω-1) to (8-n) are AND circuits, and (4-1) to (
4-4 is a memory circuit that maintains and outputs the input signal.

In addition, 5IA-5n is the output signal of various relays, Kl"
-Kn is a monitoring failure signal, and in the figure, A and B indicate signal detection points.

FIG. 2 is a time chart showing signal states of the monitoring circuit.

Next, the operation will be explained with reference to the time chart shown in FIG. The lines 81e and 1% Kl,'s e'' in FIG. 2 show the corresponding signal waveforms in FIG. 1.The relay remains stationary and in a waiting state most of the time.

If a short circuit or ground fault occurs somewhere in the power system, or if abnormal operation occurs that destroys power equipment or adversely affects other parts of the power system, Issue an order to immediately disconnect the part from the grid.

When the breaker connected to the faulty part is tripped by the command output signal and the faulty part is disconnected from the grid,
The relay returns to its normal state and the output signal disappears. Therefore, the output signal (in this case, whether the relay was activated due to a failure in the power system or due to a failure in the relay itself)
A timer circuit (2) is used to determine whether a continuous signal (which is considered to be a continuous signal) has occurred.

When the relay S1 malfunctions and the output signal S1 becomes a continuous signal, the output A of the OR circuit (1) becomes ``H'', and the output B becomes "H" after the operating time T1 of the timer circuit (2).

This output B becomes the gate signal for the AND circuit Pa(a-t), and since the signal S1 is @H, the output of the AND circuit (a-t) becomes ・H・, and the next stage memory circuit (4-1) The output is maintained at "H". That is, when 1 is output as the defective signal, it is detected that the relay S1 is at fault, and an alarm is issued.

Here, the operating time Tl of the timer circuit (2) is set by adding a small allowable value to the time it takes for the breaker to trip in the event of a failure in the power system and for the relay to return to normal operation. In addition, the memory circuits (4-1) to (4→) are detected to be defective due to malfunction of the relay, and then the output signal S1"8 is detected due to defective recovery, etc.
If n disappears, the cause of the alarm may become unknown, so this is provided to leave evidence of defect detection.

Therefore, (if the relay operates normally due to a failure in the power system, the duration of the operation output is less than the operation time T1 of the timer circuit (2), so the output B of the timer circuit (2) and the AND circuit ( 8-1) ~ω-→ output is 1°
L” and no alarm is issued.

However, for example, relay St malfunctions and output signal 1S1
When the relay S2 detects a failure in the power system and outputs the output signal S2 while the operation is continuing, the output B of the timer circuit (2) due to the output signal S1 is generated only by the gate signal of the AND circuit (8-1). Since the gate of the AND circuit ω- is also open, the failure detection signal S2 of the system is transmitted to the memory circuit (
4-2), and it is erroneously determined that the output is due to a malfunction of the relay 5.

Conventional monitoring circuits are configured to input the output signal of a relay through an OR circuit so that it can be identified by a single timer circuit. Therefore, after an erroneous output from a malfunctioning relay, all output signals from other relays are erroneous. There was a drawback that it could be misjudged as being an output, causing the problem to jump.

This invention was made for the purpose of eliminating the drawbacks of the conventional ones as described above.After detecting a monitoring failure due to an erroneous output, the monitoring circuit is prevented from inputting this erroneous output to the monitoring circuit. The present invention provides a monitoring circuit that can detect defects without error.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 8, (5-1) to (5-n) are inhibit circuits forming inhibition circuits. FIG. 4 is a time chart showing signal states of the embodiment.

In FIG. 4, the waveforms of the corresponding portions in FIG. 8 are shown.

Next, the operation of the embodiment will be explained. When relay 5 malfunctions and the output signal & becomes a continuous signal, the inhibit circuit Cs-1) opens its gate as an initial state, so O
The output A of the R circuit +1) becomes H", and the timer circuit (2
) After the operating time Tl, the output B of the timer circuit (2) is
It becomes H. This output B becomes the gate signal of the AND circuit (ω-1), and since the signal S1 is ・H・, the AND circuit (8
-1) becomes ・H・ and the next stage memory circuit (4-
1) maintains the output H. Memory circuit (4-1)
At the moment when the inhibit circuit (5-1) is activated, the inhibit circuit (5-1) closes the gate and prevents the output signal St from being input to the timer circuit (2). For example, when relay 5 malfunctions and continues output signal 5, even if relay S2 detects a failure in the power system and outputs output signal S2, a monitoring failure due to output 48 @ s is detected. At this point, the input of the output signal S1 to the timer circuit (2) is blocked, so the output signal S2 due to the normal operation of the relay is shorter than the operating time T1 of the timer circuit (2), so the memory (4-) is Not energized. Furthermore, it can be seen that even if the output signal 5 is generated within the operating time 1 after the erroneous output signal 5, the monitoring circuit operates normally. Note that in the event that the relay operates normally due to a system failure, no alarm is generated because the duration of the output signal is shorter than the operating time T1 of the timer circuit. This point is similar to the conventional circuit.

As described above, according to the present invention, since the input signal to the timer circuit is blocked after the input signal continues for a certain period of time, it is possible to obtain a monitoring circuit whose detection results are reliable.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional monitoring circuit, FIG. 2 is a time chart of waveforms of each part of FIG. 1, FIG. 8 is a circuit diagram showing an embodiment of a monitoring circuit according to the present invention, and FIG. 8 is a time chart showing the waveforms of each part in FIG. In the figure,
(1) is an OR circuit, (2) is a timer circuit, (8-1
) to (8-n) are AND circuits, (4-1) to (4-n
) is a memory circuit, and (5-1) to (5-n) are inhibit circuits. Also, Sl”-5n is the output signal of the relay, Kl
~Kn is a defective signal, and A and B are signal detection points. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
: Agent Shin Kuzuno - Figure 1 Figure 2

Claims (1)

[Claims] a timer circuit that detects that any one of the plurality of input signals continues for a certain period of time; and a timer circuit that is provided corresponding to each of the input signals and is activated by the timer circuit when the corresponding input signal continues for the certain period of time. A monitoring circuit comprising a plurality of memory circuits and an inhibit circuit that blocks input of a corresponding input signal to the timer circuit when any of the memory circuits is activated.