JPS59230380A - Reference level adjusting device of video signal - Google Patents

Abstract

PURPOSE:To reduce the fluctuation of the gain of an FM modulator by controlling a transmission frequency and a gain by the 1st and 2nd error signal obtained by comparing two signal components of a video recording signal with different reference frequency respectively. CONSTITUTION:The N-channel of video signals S31-S3N are transmitted to frequency-gain automatic adjusting circuits 121-12N via a serial-parallel converter 11 from a video signal S1 incoming from a camera 3. The video signal S31 of the 1st channel is given to an FM modulating circuit 16 via a gain control circuit 15, this FM modulation output is transmitted as a recording signal S21 of the 1st phase and applied to an automatic frequency adjusting circuit 17 and an automatic gain adjusting circuit 18. The carrier frequency of the 1st phase recording signal S21 is adjusted automatically by an output of the automatic frequency adjusting circuit 17, the output of the automatic gain adjusting circuit 18 is fed back to the gain control circuit 15 so as to adjust automatically the level of the 1st phase recording signal S21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference level adjustment device for a video signal, and is particularly suitable for application to a television signal processing device.

[Background technology and its problems]

In a video tape recorder (VTR) as a television signal processing device, the video signal is generally frequency modulated (FM: iLiMl) to convert the video signal into a low frequency range and convert the video signal into low frequency signals as time passes during one horizontal opening period H. A signal exhibiting frequency changes as shown in FIG. 1 is recorded on tape. The video signal in Figure 1 is of type C format (NTSC), and a frequency FP of 7.9 (Ml(z)) is assigned to the pedestal level LP, and a frequency FP of 7.9 (Ml(z)) is assigned to the change level LH of the horizontal synchronizing signal H8. A frequency FH of 7-06[:MHz] is assigned, and the frequency is changed in the direction of increasing the frequency from the pedestal level LP in accordance with the change in the amplitude of the video signal VD.

(2) In conventional VTRs that record FM-modulated video signals on tape as a recording medium, the frequency corresponding to the pedestal level LP is adjusted to a predetermined frequency using an automatic frequency control loop (AFC loop). By fixing it, an idea has been made to improve the reproducibility of the image.

However, in a signal processing device in which this type of video signal is processed by multiple FM modulators, if there are any asthmatic variations in each FM modulator, the frequency of the video recording signal may be adjusted to the pedestal frequency FP'&center. Direction of increase/decrease (
This results in variations in the gain direction. If there are variations in frequency in the gain direction, in a processing device that combines a plurality of FM modulated video signals to obtain a reproduced image, even if the pedestal frequency matches, the scale in the gain direction does not match. reproducibility may deteriorate.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and is based on FMiH
The objective is to ensure that the scale in the gain direction of the video signal obtained does not vary even if there are variations in the FM modulator.

[Summary of the invention]

In order to achieve this object, the present invention demodulates the first signal portion of the video recording signal and the tenth base frequency signal into level signals, compares the levels of the two, and detects the first error as a result of the comparison. an automatic frequency adjustment circuit that controls the oscillation frequency of the frequency modulation circuit according to the signal; and an automatic frequency adjustment circuit that demodulates the second signal portion of the video recording signal and the second fundamental frequency signal into a level signal and compares the levels of the two. By providing an automatic gain adjustment circuit that controls the gain of the gain control circuit using a second error signal as a result of the comparison, it is possible to maintain the fundamental frequency of the video recording signal at a predetermined value and to prevent frequency changes in the gain direction. is also maintained at a predetermined value.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a high-speed phenomenon recording device 2 having the multiphase recording signal generation circuit 1 shown in FIG. 3 as a television signal processing device. A video code 81 having a single television system format, for example, type C format (NTSC)' is applied to the polyphase recording signal generation circuit 1, which generates the video code of each field sequentially transmitted from the camera 3 in time series. The data is converted into a parallel year number 82] to s2N of a plurality of N channels (for example, 5 channels) and sent to the multi-channel VTR 4. The VTR 4 sequentially records N-channel video signals onto diagonal tracks on a tape using N rotary video heads provided for each channel, and records N-phase video signals on these serially recorded tracks into N-channel video signals. By performing slow motion reproduction using the video heads, the high speed phenomenon imaged by the camera 3 can be converted into a slow motion video signal.

The polyphase recording signal generation (b) path 1 (FIG. 3) receives the video signal 81 coming from the camera 3 into a serial-to-parallel converter 11 having a 7' yield memory (consisting of 2 x N) of 7'kN channels. . Each channel is assigned a pair of field memories such that each field of video signal arriving in a time plane sequence is written to one field memory of each channel while being stored in the other field memory of each channel. By reading out the video signals all at once, N-channel video signals 831-83N are sent to frequency-gain automatic adjustment circuits 121-12N, respectively.

Here, the serial-parallel converter 11 includes a synchronization signal generation circuit 13.
The horizontal synchronizing signal S4 generated in the video signal S1 is inserted into the video signal S1 to generate video signals S31 to S31 in the same signal format as described above with respect to FIG.
53Na/. Here, the level of the horizontal synchronizing signal H8 is increased to a predetermined value with respect to the pedestal level LP, and thereby each video signal 821 to 82N
Horizontal XJIG with respect to pedestal level LP at
The level ratio of No. H8 is made to be the same.

Each of the automatic adjustment circuits 121 to 12N has the same configuration, and therefore, in FIG. 3, the detailed configuration of the automatic adjustment circuit 121 of the first channel will be described.

That is, the first channel video signal S31 sent from the serial-parallel converter 11 is given to the FM modulation circuit 16 via the gain control circuit 15, and the FM modulation circuit 16
The FM variable expansion output is sent out as the first phase distribution signal S21, and is also given to the automatic frequency adjustment circuit 17 and the automatic gain adjustment circuit 18.

The automatic frequency adjustment circuit 17 adjusts the pedestal level LP (FIG. 4(A)) of the first phase recording signal 821 and the Q-destal frequency FP to a first reference value (for example, 7.9 [■z)]. The first phase recording signal 821 is received by the RFF switch path 21. A pedestal frequency signal S4 sent from the pedestal frequency signal generation circuit 19 is applied to the RFF switch path 21 as a first basic signal, and
A switch timing signal S51 is provided. As a result, as shown in FIG. 4 ω), the RF
The first phase recording signal 821 is passed through the F switch path 21, and the first phase recording signal 821 is passed through the other section T2.
is adapted to pass the pedestal frequency signal S4 through the RFF switch path 21.

The output s6 of the RFF switch path 21 is crushed in the demodulation circuit n, converted into a DC level signal, and then applied to the analog switch circuit B. The analog switch circuit η switches according to the switch timing signal 86] and outputs the first phase recording signal 521 (fourth phase recording signal 521) as shown in FIG.
When the signal (A) is in the pedestal section T1, as shown in FIG. When the recording signal S21 is in the other section T2, the demodulated level signal is sent to the pedestal riot signal sample hold circuit 24 B fl11
' to hold the DC level.

The DC level signals sensed and held in the sample and hold circuits 2AA and 24B are compared in a comparator circuit 5 having a differential amplifier circuit configuration, and an error signal S representing the deviation is generated.
7 is fed back to the FM modulation circuit 16 as an automatic frequency control signal (AFC signal), and by adjusting the carrier of the first phase recording signal 821, the pedestal frequency FP is adjusted to K (that is, F
Adjust self-illumination 1 so that P = 7.9CM (z).

Further, the automatic gain adjustment circuit 18 adjusts the frequency corresponding to the signal level LH (FIG. 4(A)) of the horizontal synchronizing signal H8 of the first phase recording signal S21 to a second reference value (for example, 7.06 CM).
tb:) ), automatic frequency control signal 1
Similarly to 7, the first phase recording signal 821 is received by the RF switch circuit. The RF switch circuit pressure is supplied with a synchronous frequency signal S7 sent out from a synchronous frequency signal generation circuit, as well as a switch timing signal S81.

As a result, the first phase recording signal 521 as shown in FIG.
(Fig. 4(A)) is in the horizontal synchronization signal section T3, the RF
The first phase recording signal 821 is passed through the F switch circuit n, and when the first phase recording number 821 is in the other section T4, the synchronous frequency signal S7 is passed through the RF switch circuit Z7'lz: being done.

The output of the RF switch circuit γ is demodulated in a demodulation circuit 4, converted into a DC level signal, and then applied to an analog switch circuit (9). The analog switch circuit (9) switches according to the switch timing signal 891 and outputs the first phase recording signal 521 (41st phase) as shown in FIG.
19(A)) is in the horizontal synchronization (interval i section T3), the sample and hold circuit 3 for synchronization detection signal outputs the signal level signal.
1Af1[ to hold its DC level, and when the cut first phase recording signal S21 is in a section other than that T4, the demodulated level signal is passed through the synchronization base ring signal sample hold circuit 31B extension to hold its DC level. Hold the level.

The DC level signals held in the sample and hold circuits 31A and 31B are compared in a comparison circuit 32 having a differential amplifier circuit configuration, and an error signal SIO representing the deviation is sent to the gain control circuit 15 as an automatic gain control signal (AGC signal). Feedback is given and this causes the first
Frequency F corresponding to the synchronization signal level of the phase recording signal 821
so that the H'l error signal 810 becomes 0 (i.e., F
Automatically adjust so that H = 7.06 (MHz).

In the above configuration, the video signal S1 sent from the camera 3 is converted into parallel video signals 831 to 83N for each field in the serial-to-parallel converter 11.
~Nth channel frequency-gain automatic adjustment circuit 121
~12N is given. Each of the frequency-gain automatic adjustment circuits 121 to 12N operates as described above for a) i and [F] in FIG. After the recording signals 821 to 82N are given to the reproducing circuit 4 and decoded, they are held in the sample hold circuit 31A via the analog switch circuit 30. Also the fourth
As described above with respect to the figures (Bl and C), recording (when iW numbers 821 to 82N reaches the pedestal section T1, the automatic cycle mantissa adjustment circuit 170 is applied to the strawberry adjustment circuit wr22 through the RF switch circuit 21 and demodulated, and then the analog switch circuit The automatic frequency adjustment circuit 17 supplies the pedestal reference signal S4 to the demodulation circuit B through the RF switch circuit 21 in a section T2 other than the section T1, demodulates it, and then switches it to the analog switch. The automatic level adjustment circuit 18 outputs the synchronization reference signal S7 to the Yasu circuit through the RF switch circuit γ in the interval T4 other than the interval T3. 4 and demodulated, then the analog switch circuit 3
0 to the sample hold circuit 31B (FIG. 4).
~12N all at once hold the first reference value of the level corresponding to the reference pedestal frequency in the sample and hold circuit 24B, and also hold the second reference value corresponding to the lf station frequency. The comparison circuits 25 and 32 compare the outputs of the sample and hold circuits 24A and 31A, respectively.
Pedestal frequency FP of N-phase recording signal 121 to 12N
and adjust the horizontal synchronizing signal level frequency F'H.

As a result, for the first to Nath recording signals S21-82N, the pedestal frequency PF is set to the frequency of the reference pedestal frequency signal s4 common to all channels? A, please be in order,
Similarly, the frequency corresponding to the level LH of the N-period double H8 is the island J of the riot synchronization same wave number signal S7 common to all channels.
adjusted to the wave number. This means that the polyphase recording signal 821~
This means that the scale in the gain direction based on the pedestal frequency 11FP of 82N is obtained at the same value of 1. Therefore, the first to second phase recording signals S21-82N are formed diagonally so as to be sequentially adjacent to each other. By recording on a large number of tracks, the reproducibility of the image can be improved during slow motion playback by scanning the head across the large number of tracks. Since the level can be adjusted for each horizontal synchronization section when sniffing, accuracy can be increased. Incidentally, this is because there is less change in data during the sample hold time and the number of samples per time is greater than when level adjustment is performed for each vertical synchronization period.

In the case of the embodiment shown in FIG. 3, the structure shown in FIG. 5 is used as the 1n column-to-parallel converter 11. That is, the input video signal S1 arriving from camera 3 is analog (13)
,^^- After being digitally converted in the digital conversion circuit 41, the synchronization signal insertion circuit 42
A basic horizontal synchronizing signal S4 is inserted thereinto and applied to the serial-to-parallel converter circuit 43. Here, synchronization signal generation circuit 1
3 sends out a horizontal synchronizing signal 84'2 which represents the level of the synchronizing signal as a digital value. The parallel outputs 8111 to S LIN of the partial sequence-to-parallel conversion circuit are each digital.
After analog conversion in analog conversion circuits 441 to 44N, modulation circuits 451 to 45N and amplifier circuit 461
1st to Nth channel video signals 8 through ~46N'e
31 to 83N.

With this configuration, the first to Nth channel video signals 831 to 83N sent out from the serial-parallel converter 11
The relationship between the pedestal level of the video signal S1 and the horizontal synchronization signal level is the relationship between the pedestal level of the video signal S1 arriving from the camera 3 and the horizontal synchronization signal S inserted into this video signal S].
It will be determined uniformly depending on the relationship with level 4. Therefore, the relationship between the synchronizing signal level frequency and the pedestal frequency in the first to N-th phase recording signals 821 to 82N (FIG. 3) can be made more precise and uniform.

6 to 8 show other embodiments of the serial-to-parallel converter 11, and in the case of FIG. 6, as shown by attaching the same number to the corresponding part to FIG. 5, a synchronizing signal insertion circuit is shown. The configuration is the same as that shown in FIG. 5, except that 42 is provided before the analog-to-digital conversion circuit 41. On the other hand, in the case of FIGS. 7 and 8, synchronization signal insertion circuits 471 to 47N are inserted to the parallel outputs 5ill-5LIN of the serial-parallel conversion (b) path 43, respectively. 7th
In the case of the figure, the parallel outputs 5111 to 5IIN are digitally connected.
The digital synchronization signal S4 is inserted before analog conversion by the analog conversion circuits 441 to 44NK,
In the case of FIG. 8, an analog synchronization signal 84 is inserted after analog conversion.

Even with the configuration shown in FIGS. 6 to 8, the same effect as described above for the fifth piece can be obtained.

In the above description, an automatic frequency adjustment loop is provided for the pedestal level 7L/LPK, and an automatic gain adjustment loop is provided for the level L)I of the horizontal synchronizing signal H8, thereby adjusting the gain direction for the pedestal level LPK. Although the level adjustment is performed in the above embodiment, the level adjustment in the gain direction may be realized using the following configuration.

First, focusing on the fact that a level signal can be inserted into the vertical blanking interval without fear of adversely affecting the video signal, first, a predetermined reference level signal is used instead of the reference horizontal synchronization signal 87 or the reference pedestal signal 84K described above. You may also insert . Second, two level signals may be inserted and these level signals may be used to automatically adjust the frequency or automatically adjust the gain vI4.

Further, in the above embodiment, automatic frequency adjustment is performed using the pedestal frequency and automatic gain adjustment is performed using the level of the horizontal synchronization signal, but the roles of each signal may be reversed.

Furthermore, in the above embodiment, the gain level adjusted by the automatic gain adjustment loop is fixed, but instead, it is made variable (for example, the output S7 of the synchronous frequency signal generation circuit section in FIG. (variable frequency)
Accordingly, the scale in the gain direction of the first to Nth phase recording signals 821 to 82N may be changed.

Further, a frequency-gain automatic adjustment circuit 12 having a third factor configuration
1 to 12N, the automatic frequency adjustment circuit 17 and the automatic gain adjustment circuit 18 are provided with the circuits n and 6, respectively, but instead of this, as shown in FIG. A control circuit 51 may be provided and used in a time-division manner.

In other words, in this case, the chest wave number-gain automatic adjustment circuit]21
As shown by attaching the same reference numerals to the corresponding parts as in Fig. 3,
The 1a recording signal 821 of the modulation circuit 16 is applied to the demodulation circuit 51 through the 52 RF switch circuits that are switched according to the switch timing S15, and the demodulation signal 816 is supplied to the demodulation circuit 51.
is given to an analog switch circuit which performs a switching operation according to a switch timing signal 817.

The RF switch circuit 52 is supplied with the reference signal S4 of the reference pedestal signal generation circuit 19 and the reference signal S7 of the reference synchronization signal generation circuit side, and as shown in FIG. Section Tll where H8 arrived
Then, the level is given to the demodulation circuit 51 through the RF switch circuit 52 and the demodulation output S16 is held in the synchronous detection signal sample hold circuit 31A as shown in FIG. 10 (0) through the analog switch circuit 53. The level of the first phase recording signal 82 is set by the RF' switch circuit 52 in the pedestal section T12.
through the demodulation circuit 51 and its demodulation output 51
The pedestal detection signal is held by the sample and hold circuit 24A through the 64 analog switch circuit &. Further, in the first half section T13 of the video signal section of the 1a recording signal S21, the pedestal reference single signal S4 is given to the demodulation circuit 51 through the RF switch circuit 51, and the demodulated output 816 is sent to the pedestal reference signal sample hold circuit through the analog switch circuit 53. Make 24B hold. Furthermore, in the second half section T14 of the video signal section of the first phase recording signal 821, the synchronization reference signal S7 is provided to the demodulation circuit 51 through the RF switch circuit 52, and the demodulated output 816 is sent to the synchronization reference signal sample and hold circuit through the analog switch circuit 53. 31 Hold HK.

In this way, the AFC and AGC error signals S7 and S10 can be obtained in the comparator circuits 5 and 32, respectively, so that only one OBN circuit 51'&one common to the AFC loop and the AGC loop is required.

Furthermore, FIG. 11 shows an embodiment in which only one demodulation circuit is provided in common for all channels, and frequency-gain automatic adjustment circuits 121 to 12N of the first to Nth channels are provided.
The first to Nth phase recordings of @Tan 821 to S2N are applied to the RF switch circuit, and the reference pedestal signal generation circuit t
q and the AFC and AGC basic signals 84 and S7 of the Motosu synchronization signal generation circuit are applied to the RFF switch path 55, and the switching timing described above for the RFF switch path 52 of FIG. Give the same switch timing for each issue as if time-divided for the 1st to Nth channels and made one round during one field section.

Thus, the recording signal S passes sequentially through the RFF switch path 55.
21- S2N, KAFC and AGC base revolt 84 and S7 'v are given to the post-post circuit 56 and their demodulated output is given to the analog switch circuit 57. The analog switch circuit 57 is connected to the RF signal by the switch timing No. 4i S, 19.
The switch operates in cooperation with the F switch path 55 to send the demodulated output to the AFC sample and hold circuit 2 of the first channel.
4A and 24B, the AGC sample and hold circuits 31A and 3'lB, and the A and FC sample hole 1 circuits 24h and 24B of the Nth channel, and the AGC sample and hold circuits 3fA and BIB.

Even if this is done, the AFC and AGC error number S7 of the 1st to Nth channels will be the same as in the bare 2nd case of FIGS. 3 and 9.
and 810 can be obtained, and thus only one demodulation circuit 56 needs to be provided in common for the first to Nth channels.

〔Effect of the invention〕

As described above, according to the present invention, a signal portion having a first reference frequency is created in a recorded video signal, and a signal portion having a second reference frequency in the gain direction with respect to the first reference frequency is created. By creating this, it is possible to obtain a frequency modulated video signal with good image replayability.

[Brief explanation of the drawing]

FIG. 1 is a signal waveform diagram showing a frequency-positioned video signal, FIG. 2 is a block diagram showing a high-speed phenomenon recording device, and FIG. 3 is a block diagram showing an example of a standard level adjustment device for video year numbers according to the present invention. Fig. 4 is a route diagram showing the operation of the switch circuit, Fig. 5 is a block diagram showing the detailed configuration of the series-parallel converter shown in Fig. 3, and Figs. 9 is a block diagram showing another embodiment of the frequency-gain automatic adjustment circuit of FIG. 3; FIG. 10 is a route diagram showing the operation of the switch circuit; FIG. 11 is a block diagram showing another embodiment of the frequency-gain automatic adjustment circuit of FIG. FIG. 2 is a block diagram showing another embodiment of the switch circuit. DESCRIPTION OF SYMBOLS 1... Multiphase recording signal generation circuit, 2... High-speed phenomenon recording device, 3... Camera, 4... VTR%11--Series-parallel converter, 121-12N... Frequency-gain Automatic adjustment circuit, 15...gain control circuit, 16...-F
M modulation circuit, 17... automatic frequency adjustment circuit, 18...
- Automatic gain adjustment circuit, 19...-pedestal frequency signal generation circuit, road... synchronous frequency signal generation circuit. Applicant's representative 1) Megumi Be, Procedural amendment dated January 1980, □ Mr. Kazuo Wakasugi, Director-General of the Office 1 1. Indication of the case Showa Patent Application No. 106190 2. Name of the invention Video signal standards Level V@Adjustment Equipment 3, Relationship with the Person Who Requests Amendment Case Patent Applicant Address 6-7 Kitashinyo, Parts Ward, Tokyo Name of Department (218)
) Sony Corporation Representative Norio Oga 4, Agent Address: 150 (Telephone 03-470-6591)
)Address 3-n-10-5, Jingumae-3, Shibuya-ku, Tokyo, page 6 of the "Detailed Description of the Invention" in the Specification Subject to Amendment, Contents of Amendment (1) Specification, page 2, lines 9-10, [ Perform low frequency conversion and delete 1 digit. (2) Same, page 2, lines 2-4, ``The standard television format...'' has been deleted. (3) Same, 5th negative line, 14th line, 1N 'n' and '1 and more!' is corrected. (4) Ibid., page 20, line 17, insert the following statement after "It's fine if it is provided.""In this case, there is only one demodulator, so the errors between each n channel and AGC and AFC are minimized." (2)

Claims (1)

[Scope of Claims] A television signal processing circuit configured to frequency-modulate an input video signal applied to a frequency modulation circuit through a gain control circuit to obtain a video recording signal to a recording medium. an automatic frequency adjustment circuit that demodulates the first signal portion and the first reference frequency signal into a level signal, compares the levels of both, and controls the oscillation frequency of the frequency modulation circuit using a first error signal as a result of the comparison; Then, the second signal portion of the video recording signal and the second reference frequency signal are demodulated into a level signal, the levels of both are compared, and a second error signal as a result of the comparison is used to control the gain control circuit. An automatic gain adjustment circuit for controlling gain is provided. 1 yen: A video signal reference level adjustment device characterized by: (1),
Wa [