JPH0524713B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference level adjustment device for a video signal, and is particularly suitable for application to a television signal processing device.

[Background technology and its problems]

In a video tape recorder (VTR) as a television signal processing device, the video signal is generally frequency modulated (FM modulated) so that the video signal is processed as shown in FIG. 1 over time during one horizontal synchronization period H. It is designed to record signals exhibiting frequency changes on tape. The video signal in Figure 1 is of type C format (NTSC), with a frequency FP of 7.9 [MHz] assigned to the pedestal level LP, and a horizontal synchronization signal HS.
Frequency of 7.06 [MHz] for change level LH
FH is assigned, and a change in frequency corresponding to a change in the amplitude of the video signal VD is caused in the direction of increasing the frequency from the pedestal level LP.

In conventional VTRs that record FM-modulated video signals on tape as a recording medium, the frequency corresponding to the pedestal level LP is fixed at a predetermined frequency using an automatic frequency control loop (AFC loop). Efforts have been made to improve image reproducibility.

However, in a signal processing device that processes this type of video signal using multiple FM modulators, if there are variations in the characteristics of each FM modulator, the frequency of the video recording signal will be adjusted around the pedestal frequency FP. This results in variations in the direction of increase and decrease (this is called the gain direction). If there are variations in frequency in the gain direction, multiple FM
In a signal processing device that combines modulated video signals to obtain a reproduced image, even if the pedestal frequencies match, the scales in the gain direction do not match, so there is a risk that image reproducibility may deteriorate.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and
The objective is to ensure that the scale in the gain direction of an FM modulated video signal does not vary even if there are variations in the FM modulator.

[Summary of the invention]

In order to achieve this purpose, the present invention includes:
The first signal portion of the video recording signal and the first reference frequency signal are demodulated into level signals, the levels of both are compared, and the oscillation frequency of the frequency modulation circuit is determined by the first error signal as a result of the comparison. an automatic frequency adjustment circuit to control and a second
an automatic gain adjustment circuit that demodulates the signal portion and the second reference frequency signal into a level signal, compares the levels of both, and controls the gain of the gain control circuit using a second error signal as a result of the comparison; By providing this, the reference frequency of the video recording signal is maintained at a predetermined value, and the frequency change in the gain direction is also maintained at a predetermined value.

〔Example〕

An embodiment according to the present invention will be described in detail below with reference to the drawings. FIG. 2 shows a high-speed phenomenon recording device 2 having the multiphase recording signal generation circuit 1 shown in FIG. 3 as a television signal processing device. Applying the signal S1 to the multiphase recording signal generation circuit 1,
In this way, the video signals of each field, which are sent out in time series from the camera 3, are converted into parallel signals S21 to S of a plurality of N channels (for example, 5 channels).
Convert to 2N and send to multi-channel VTR4. The VTR 4 sequentially records N channels of video signals on diagonal tracks on a tape by N rotating video heads provided for each channel, and records the video signals of N phases of this series of recording tracks into one. By performing slow-motion reproduction using the individual video heads, the high-speed phenomenon imaged by the camera 3 can be converted into a slow-motion video signal.

The multiphase recording signal generation circuit 1 (Fig. 3) is connected to the camera 3.
A video signal S1 arriving from the video signal S1 is received by a serial-to-parallel converter 11 having N-channel field memories (consisting of 2×N). Each channel is assigned a pair of field memories such that the video signal of each field arriving in time series is written to one field memory of each channel while the video signal stored in the other field memory of each channel is By reading out the signals all at once, N
Channel video signals S31-S3N are sent to frequency-gain automatic adjustment circuits 121-12N, respectively.

Here, the serial-parallel converter 11 is given a horizontal synchronizing signal S4 generated in the synchronizing signal generating circuit 13, and the horizontal synchronizing signal S4 is added to the video signal S1.
4 is inserted to obtain video signals S31 to S3N in the same signal format as described above with respect to FIG. Here, the level of the horizontal synchronizing signal HS is selected to a predetermined value with respect to the pedestal level LP, so that the ratio of the level of the horizontal synchronizing signal HS to the pedestal level LP in each video signal S21 to S2N is made to be the same. .

Each of the automatic adjustment circuits 121 to 12N has the same configuration. Therefore, in FIG. 3, the detailed configuration of the automatic adjustment circuit 121 of the first channel will be described.

That is, the first channel video signal S31 sent from the serial-parallel converter 11 is given to the FM modulation circuit 16 via the gain control circuit 15,
The FM modulation output of this FM modulation circuit 16 is sent out as a first layer recording signal S21, and is also given to an automatic frequency adjustment circuit 17 and an automatic gain adjustment circuit 18.

The automatic frequency adjustment circuit 17 receives the first layer recording signal S21.
The pedestal frequency FP corresponding to the pedestal level LP (Fig. 4A) is set to the first reference value (for example, 7.9
[MHz]), and the first layer recording signal S2
1 is received by the RF switch circuit 21. The RF switch circuit 21 includes a pedestal frequency signal generation circuit 19.
A pedestal frequency signal S4, which is sent out, is provided as a first reference signal, and a switch timing signal S51 is also provided. This allows the fourth
As shown in Figure B, during the back porch section T1 where the first layer recording signal S21 is at the pedestal level LP.
The first layer recording signal S is transmitted through the RF switch circuit 21.
21, and when the first layer recording signal S21 is in the other section T2, the RF switch circuit 2
1 to allow the pedestal frequency signal S4 to pass therethrough.

The output S6 of the RF switch circuit 21 is sent to the demodulation circuit 2.
2, the signal is demodulated and converted into a DC level signal, which is then applied to an analog switch circuit 23. The analog switch circuit 23 operates as a switch in accordance with the switch timing signal S61, and as shown in FIG. 4C, when the first phase recording signal S21 (FIG. 4A) is in the pedestal section T1, the signal is switched as shown in FIG. 4C. The demodulated level signal is passed through the pedestal detection signal sample hold circuit 24A side to hold its DC level, and the first phase recording signal S21
is in the other section T2, the demodulated level signal is sent to the pedestal reference signal sample hold circuit 2.
The DC level is held by passing it to the 4B side.

Thus sample and hold circuits 24A and 24
The DC level signals held at B are compared in a comparator circuit 25 having a differential amplifier circuit configuration, and an error signal S7 representing the deviation is fed back to the FM modulation circuit 16 as an automatic frequency control signal (AFC signal). The pedestal frequency can be adjusted by adjusting the carrier of the phase recording signal S21.
FP so that the error signal is 0 (i.e. FP
= 7.9 [MHz]).

The automatic gain adjustment circuit 18 also controls the signal level LH (fourth level) of the horizontal synchronizing signal HS of the first phase recording signal S21.
The frequency corresponding to Figure A) is set to a second reference value (e.g.
7.06 [MHz]), and similarly to the automatic frequency adjustment circuit 17, the first phase recording signal S21 is received by the RF switch circuit 27. RF switch circuit 27
is supplied with the synchronous frequency signal S7 sent out from the synchronous frequency signal generation circuit 28, as well as the switch timing signal S81. As a result, as shown in FIG. 4D, the first phase recording signal S21
(A in Figure 4) is in the horizontal synchronization signal section T3, the RF
The first phase recording signal S21 is transmitted through the switch circuit 27.
When the first phase recording signal S21 is in a period T4 other than that, the synchronous frequency signal S7 is passed through the RF switch circuit 27.

The output of the RF switch circuit 27 is demodulated in a demodulation circuit 29, converted into a DC level signal, and then applied to an analog switch circuit 30. The analog switch circuit 30 receives a switch timing signal S.
When the first phase recording signal S21 (FIG. 4A) is in the horizontal synchronization signal section T3, the demodulated level signal is transferred to the synchronization detection signal sample hold circuit 31A side as shown in FIG. 4E. to hold the DC level, and the first
When the phase recording signal S21 is in a section T4 other than that, the demodulated level signal is passed to the synchronization reference signal sample hold circuit 31B side and its DC level is held.

Thus sample and hold circuits 31A and 31
The DC level signals held at B are compared in a comparator circuit 32 having a differential amplifier circuit configuration, and an error signal S10 representing the deviation is fed back to the gain control circuit 15 as an automatic gain control signal (AGC signal). 1 phase recording signal S
The frequency FH corresponding to the synchronization signal level of 21 is set so that the error signal S10 becomes 0 (that is, FH
= 7.06 [MHz]).

In the above configuration, the video signal S1 sent from the camera 3 is converted into parallel video signals S31 to S3 for each field in the serial-parallel converter 11.
The frequencies of the 1st to Nth channels are converted to N -
It is given to automatic gain adjustment circuits 121 to 12N. Each frequency-gain automatic adjustment circuit 121-12
As described above with respect to FIGS. 4D and E, when the recording signals S21 to S2N reach the horizontal synchronization period T3, the recording signals S21 to S2N are supplied to the demodulation circuit 29 through the RF switch circuit 27 of the automatic gain adjustment circuit 18. Analog switch circuit 3 after demodulation
0 to be held by the sample hold circuit 31A. Furthermore, as described above with respect to FIGS. 4B and 4C, when the recording signals S21 to S2N reach the pedestal section T1, the automatic frequency adjustment circuit 17
The signal is supplied to the demodulation circuit 22 through the switch circuit 21 for demodulation and then held in the sample hold circuit 24A through the analog switch circuit 23. On the other hand, the automatic frequency adjustment circuit 17 supplies the pedestal reference signal S4 to the demodulation circuit 22 through the RF switch circuit 21 in an interval T2 other than the interval T1, demodulates it, and then causes the sample and hold circuit 24B to hold it through the analog switch circuit 23. Figure 4 B and C). Also, automatic level adjustment circuit 18
The synchronization reference signal S7 is sent to the demodulation circuit 2 through the RF switch circuit 27 in the interval T4 other than the interval T3.
After demodulating by giving 9, the analog switch circuit 30
The sample and hold circuit 31B holds the sample through the sample and hold circuit 31B (FIG. 4, D and E).

Therefore, each of the automatic adjustment circuits 121 to 12N simultaneously causes the sample and hold circuit 24B to hold a first reference value corresponding to the reference pedestal frequency, and also causes the sample and hold circuit 31B to hold a second reference value corresponding to the reference synchronizing signal frequency. The reference value is held and compared with the outputs of the sample and hold circuits 24A and 31A in the comparator circuits 25 and 32, respectively, and the first to Nth phase recording signals 121 to 121 are adjusted to match the first and second reference values. 12N
Adjust the vedestal frequency FP and horizontal synchronization signal level frequency FH.

As a result, the first to Nth phase recording signals S21 to S2N
is adjusted to adjust the pedestal frequency PF to the frequency of the reference pedestal frequency signal S4 common to all channels, and also adjust the frequency corresponding to the level LH of the synchronization signal HS to the frequency of the reference synchronization frequency signal S7 common to all channels. is adjusted to
This means that the scale in the gain direction based on the pedestal frequency FP of the multiphase recording signals S21 to S2N can be made the same.

Therefore, by sequentially recording the first to Nth phase recording signals S21 to S2N on a large number of tracks formed diagonally adjacent to each other, and by scanning the head across the large number of tracks, slow motion can be achieved. When playing back, it is possible to improve the reproducibility of images. In this way, the level can be adjusted for each horizontal synchronization section, so accuracy can be improved. Incidentally, this is because the change in data during the sample hold time is smaller and the number of samples per time is larger than when the level is adjusted for each vertical synchronization period.

In the case of the embodiment shown in FIG. 3, the configuration shown in FIG. 5 is used as the serial-parallel converter 11. That is, the input video signal S1 arriving from the camera 3 is digitally converted in an analog-to-digital conversion circuit 41, and then a reference horizontal synchronization signal S4 is inserted in a synchronization signal insertion circuit 42, and then provided to a serial-to-parallel conversion circuit 43. Here, the synchronizing signal generating circuit 13 sends out a horizontal synchronizing signal S4 representing the level of the synchronizing signal as a digital value. Parallel outputs S111 to S11N of the serial-to-parallel conversion circuits are digital to analog conversion circuits 441 to 44N, respectively.
After analog conversion in the modulation circuit 451
45N and amplifier circuits 461 to 46N as first to Nth channel video signals S31 to S3N.

With this configuration, the serial-parallel converter 11
The relationship between the pedestal level of the first to Nth channel video signals S31 to S3N sent from the camera 3 and the level of the horizontal synchronization signal is the relationship between the pedestal level of the video signal S1 arriving from the camera 3 and the horizontal synchronization signal inserted into this video signal S1. It is uniformly determined in relation to the level of the synchronizing signal S4. Therefore, the first
The relationship between the synchronizing signal level frequency and the pedestal frequency in the N-phase recording signals S21 to S2N (FIG. 3) can be made even more precise and uniform.

6 to 8 show other embodiments of the serial-to-parallel converter 11, and in the case of FIG. 6, as shown by assigning the same reference numerals to the parts corresponding to those in FIG.
The configuration is the same as that shown in FIG. 5, except that the analog-to-digital conversion circuit 41 is provided at a stage before the analog-to-digital conversion circuit 41. On the other hand, in the case of FIGS. 7 and 8, the parallel outputs S111~ of the serial-parallel conversion circuit 43
Synchronous signal insertion circuit 47 for each S11N
In the case of FIG. 7, the digital synchronization signal S4 is inserted before the parallel outputs S111 to S11N are converted to analog by the digital-to-analog conversion circuits 441 to 44N. In the case of FIG. 8, the analog synchronizing signal S4 is inserted after analog conversion.

Even with the configurations shown in FIGS. 6 to 8, the same effects as described above with respect to FIG. 5 can be obtained.

In the above description, by providing an automatic frequency adjustment loop for the pedestal level LP and an automatic gain adjustment loop for the level LH of the horizontal synchronizing signal HS, it is possible to adjust the level in the gay direction for the pedestal level LP. However, this level matching in the gain direction may be realized by the following configuration. First, focusing on the fact that a level signal can be inserted into the vertical blanking interval without fear of adversely affecting the video signal, first, a predetermined reference level signal is inserted in place of the above-mentioned reference horizontal synchronization signal S7 or reference pedestal signal S4. You may also insert . Second, two level signals may be inserted and these level signals may be used for automatic frequency adjustment or automatic gain adjustment.

Furthermore, in the above embodiment, automatic frequency adjustment is performed using the pedestal frequency, and automatic gain adjustment is performed using the level of the horizontal synchronization signal.
The roles of each signal may be reversed.

Further, in the above embodiment, the gain level adjusted by the automatic gain adjustment loop is fixed, but instead, it is made variable (for example, the output S7 of the synchronous frequency signal generation circuit 28 in FIG. By making the frequency variable), the scale in the gain direction of the first to Nth phase recording signals S21 to S2N may be changed.

Furthermore, in the frequency-gain automatic adjustment circuits 121 to 12N having the configuration shown in FIG. 3, the automatic frequency adjustment circuit 17 and the automatic gain adjustment circuit 18 are provided with demodulation circuits 22 and 29, respectively. As shown in FIG. 2, one demodulation circuit 51 may be provided in common for both devices in a time-division manner. That is, in this case, the frequency-gain automatic adjustment circuit 121 converts the first phase recording signal S21 of the modulation circuit 16 into the switch timing signal S, as shown with the same reference numerals attached to the corresponding parts in FIG.
RF switch circuit 52 switched by 15
is applied to the demodulation circuit 51 via the demodulation signal S1.
6 is applied to an analog switch circuit 53 which is switched by a switch timing signal S17.

The RF switch circuit 52 is supplied with the reference signal S4 of the reference pedestal signal generation circuit 19 and the reference signal S7 of the reference synchronization signal generation circuit 28, and as shown in FIG. 10B, the horizontal synchronization signal HS of the first phase recording signal S21 is In the interval T11 where the
At the same time, the demodulated output S16 is held by the synchronization detection signal sample and hold circuit 31A through the analog switch circuit 53 as shown in FIG. 10C. Further, in the pedestal section T12 of the first phase recording signal S21, the level thereof is applied to the demodulation circuit 51 through the RF switch circuit 52, and the demodulated output S16 is applied to the analog switch circuit 53.
The pedestal detection signal sample and hold circuit 24A holds the signal through the pedestal detection signal. Furthermore, the first half section T13 of the video signal section of the first phase recording signal S21
Then, the pedestal reference signal S4 is applied to the demodulation circuit 51 through the RF switch circuit 52, and the demodulated output S16 is held in the pedestal reference signal sample and hold circuit 24B through the analog switch circuit 53. Further, in the second half section T14 of the video signal section of the first phase recording signal S21, the synchronization reference signal S7 is sent to the RF switch circuit 52.
The demodulated output S16 is sent to the demodulation circuit 51 through the analog switch circuit 53 and held in the synchronization reference signal sample and hold circuit 31B.

In this way, the AFC and AGC error signals S7 and S10 can be obtained in the comparison circuits 25 and 32, respectively, and the demodulation circuit 51 can be used in common for the AFC loop and the AGC loop.
Just set one up.

Furthermore, FIG. 11 shows an embodiment in which only one demodulation circuit is provided in common for all channels, and the first to Nth frequency-gain automatic adjustment circuits 121 to 12N of the first to Nth channels are provided. The phase recording signals S21 to S2N are supplied to the RF switch circuit 55, and the AFC and AGC reference signals S4 and S7 of the reference pedestal signal generation circuit 19 and the reference synchronization signal generation circuit 28 are supplied to the RF switch circuit 5.
5, a switch similar to that in which the switching timing described above for the RF switch circuit 52 of FIG. 9 is time-divided for the first to Nth channels and made to complete one cycle during one field section using the switch timing signal S18. Give a timing signal.

In this way, the recording signals S21 to S2N and the AFC and AGC reference signals S4 and S7, which pass through the RF switch circuit 55 in sequence, are applied to the demodulation circuit 56, and the demodulated output is applied to the analog switch circuit 57. The analog switch circuit 57 switches in cooperation with the RF switch circuit 55 according to the switch timing signal S19, and sends the demodulated output to the AFC sample and hold circuits 24A and 24B of the first channel.
AGC sample hold circuit 31A and 31B~
Nth channel AFC sample and hold circuit 2
4A and 24B, AGC sample hold circuit 3
1A and 31B are sequentially held.

Even in this way, the AFC and AGC error signals S7 and S10 of the first to Nth channels can be obtained as in the case of FIGS. 3 and 9. It is sufficient to provide only one common channel. Also, since there is only one demodulator at this time, errors between each channel and between AGC and AFC are minimized.

〔Effect of the invention〕

As described above, according to the present invention, a signal portion having a first reference frequency is created in a recorded video signal, and a signal portion having a second reference frequency in the gain direction with respect to the first reference frequency is created. By creating a loop, a frequency-modulated video signal with good image reproducibility can be obtained.

[Brief explanation of drawings]

FIG. 1 is a signal waveform diagram showing a frequency modulated video signal, FIG. 2 is a block diagram showing a high-speed phenomenon recording device, and FIG. 3 is a block diagram showing an example of a video signal reference level adjusting device according to the present invention. Fig. 4 is a schematic diagram showing the operation of the switch circuit, Fig. 5 is a block diagram showing the detailed configuration of the serial-parallel converter shown in Fig. 3, and Figs. 9 is a block diagram showing another embodiment of the frequency-gain automatic adjustment circuit of FIG. 3, FIG. 10 is a schematic diagram showing the operation of the switch circuit, and FIG. 11 is a block diagram showing another embodiment of the frequency-gain automatic adjustment circuit of FIG. FIG. 2 is a block diagram showing another embodiment of the switch circuit. DESCRIPTION OF SYMBOLS 1...Multiphase recording signal generation circuit, 2...High speed phenomenon recording device, 3...Camera, 4...VTR, 11...
...Series-parallel converter, 121-12N...Frequency-gain automatic adjustment circuit, 15...Gain control circuit, 16...FM modulation circuit, 17...Automatic frequency adjustment circuit, 18...Automatic gain adjustment circuit, 19 …
...Pedestal frequency signal generation circuit, 28...Synchronized frequency signal generation circuit.

Claims (1)

[Scope of Claims] 1. A serial-parallel converter that inserts a horizontal synchronization signal obtained from a synchronization signal generation circuit into a pedestal level section of an input video signal and converts it into a plurality of channel video signals, and each of the above channel video signals. a plurality of automatic adjustment circuits each transmitting a video recording signal to be gain-controlled and frequency-modulated to be recorded on a recording medium; a pedestal frequency signal generation circuit that generates a pedestal frequency signal and is provided in common to the plurality of automatic adjustment circuits; a synchronous frequency signal generating circuit that generates a synchronous frequency signal and is provided in common to the plurality of automatic adjustment circuits, and each of the plurality of automatic adjustment circuits has a gain control circuit that controls the gain of the corresponding channel video signal; a frequency modulation circuit that frequency-modulates the output signal of the gain control circuit and sends it out as the video recording signal; and the first (or second) signal portion and the pedestal frequency signal generation circuit (or the synchronous frequency signal generation circuit). automatic frequency adjustment that demodulates the pedestal frequency signals (or the synchronous frequency signals) of ) into DC level signals and then compares them with each other, and controls the oscillation frequency of the frequency modulation circuit using a first error signal obtained as a result. circuit, and after demodulating the synchronous frequency signal (or the pedestal frequency signal) of the second (or first) signal portion and the synchronous frequency signal generation circuit (or the pedestal frequency signal generation circuit) into a DC level signal. An apparatus for adjusting a reference level of a video signal, comprising: an automatic gain adjustment circuit that compares the results with each other and controls the gain of the gain control circuit using a second error signal obtained as a result.