JPS59229858A - バイポ−ラ形半導体装置 - Google Patents

バイポ−ラ形半導体装置

Info

Publication number
JPS59229858A
JPS59229858A JP58104260A JP10426083A JPS59229858A JP S59229858 A JPS59229858 A JP S59229858A JP 58104260 A JP58104260 A JP 58104260A JP 10426083 A JP10426083 A JP 10426083A JP S59229858 A JPS59229858 A JP S59229858A
Authority
JP
Japan
Prior art keywords
layer
region
type
transistor
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58104260A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0426223B2 (enrdf_load_stackoverflow
Inventor
Akira Kawakatsu
川勝　章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP58104260A priority Critical patent/JPS59229858A/ja
Publication of JPS59229858A publication Critical patent/JPS59229858A/ja
Publication of JPH0426223B2 publication Critical patent/JPH0426223B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • H10D84/652—Integrated injection logic using vertical injector structures

Landscapes

  • Bipolar Integrated Circuits (AREA)
JP58104260A 1983-06-13 1983-06-13 バイポ−ラ形半導体装置 Granted JPS59229858A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58104260A JPS59229858A (ja) 1983-06-13 1983-06-13 バイポ−ラ形半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58104260A JPS59229858A (ja) 1983-06-13 1983-06-13 バイポ−ラ形半導体装置

Publications (2)

Publication Number Publication Date
JPS59229858A true JPS59229858A (ja) 1984-12-24
JPH0426223B2 JPH0426223B2 (enrdf_load_stackoverflow) 1992-05-06

Family

ID=14375958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58104260A Granted JPS59229858A (ja) 1983-06-13 1983-06-13 バイポ−ラ形半導体装置

Country Status (1)

Country Link
JP (1) JPS59229858A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5361981A (en) * 1976-11-16 1978-06-02 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5361981A (en) * 1976-11-16 1978-06-02 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0426223B2 (enrdf_load_stackoverflow) 1992-05-06

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