JPS59229791A - Memory device - Google Patents

Abstract

PURPOSE:To decrease the number of precharging circuits by connecting both of paired data lines to a sense amplifier respectively. CONSTITUTION:A precharging MOSTQP which is connected to each data line and a sense amplifier PA is omitted among plural MOSTQP. For this purpose, a driver 10A delivers the voltage of a high level to lines 32 and 34 in a precharging period and then delivers the voltage corresponding to the high and low levels of address signals a0 and a0 to the line 32 and 34 after said precharging period. With use of such driver 10A, MOSTQ01, Q01, Q02, Q02, Q11, Q11, Q12 and Q12 are turned on in the precharging period. Therefore the MOSTQP connected to the amplifier PA can precharge data lines D0 and D1 as well as the drains of MOSTQA and QB of the amplifier PA respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a high-density memory, and particularly to a dynamic memory using MOS transistors (hereinafter referred to as MO8T).

[Background of the invention]

In a conventional dynamic memory using MO8T, a memory cell consists of one NMO8T and a charge storage capacitor connected to this. Advances in semiconductor integrated circuit technology have required the dimensions of memory cells to become smaller and smaller. As memory cell dimensions decrease, the signal amplitude read from the memory cell becomes smaller. Therefore, sense amplifiers for detecting signals from memory cells are required to have increasingly high performance, and as a result, they have to occupy a large amount of space. Conventionally, a large number of memory cells are connected to a pair of data lines, and a sense amplifier for differentially amplifying the voltages of these data lines is connected to the pair of data lines. A memory is constructed by arranging a large number of such structures.

In such conventional memories, the size of the sense amplifier is larger than the size of the memory cell, so even if the memory cell size is reduced, the interval between data lines connected to different sense amplifiers cannot be reduced.

Therefore, it is difficult to arrange a large number of memory cells on one semiconductor substrate. In particular, as mentioned above,
When using a memory cell of a very small size, the sense amplifier cannot be made small because it is required to have high performance. Therefore, even if the memory cell size is reduced, the data line spacing cannot be reduced. This solves the problem of the conventional technology, such as the distance between the data lines, which cannot be reduced even if the memory cell size is reduced. The technique of the original application is a technique that can reduce the interval between the two.

This new technology installs two amplifiers with different functions, one amplifier for reading memory information and one amplifier for refreshing, for two data line pairs. When one set of data line pairs is connected to a read amplifier, the other set of data line pairs is connected to a refresh amplifier.

In FIG. 1, a plurality of word lines W are shown parallel to each other and close to each other. , Wo, . . . A pair of dummy word lines DW, DW are provided orthogonally to each other, and sense amplifiers PA, PA each consisting of a flip-flop are connected to the left and right sides of these data lines. Word line W. And the data line. A memory cell MC is provided at the intersection with the word line W.

and data line. A memory cell MC is provided at the intersection with , Dl. In this way, the memory cell MC is connected to only one of the two intersections between each data line pair and each word line. Similarly, a pair of dummy word lines DW,
A dummy cell DC is provided only at one of the two intersections between DW and each data line pair. The same applies to other data lines and word lines that are not shown. In this way, 1
Memory cells (
The technology for providing (including dummy cells) is described in US Patent No. 4.04.
4.340.

To simplify the explanation, a memory using an N-channel MO8T will be explained below, but a memory using a P-channel MO8T can also be applied by changing the polarity of the voltage.

The memory cell Me is a known transistor type memory cell consisting of one MO8T and a capacitance for storing information, and the dummy cell DC is a transistor-type memory cell consisting of one MO8T and a capacitance for storing reference voltage, and is connected in parallel to this capacitance. This is a known dummy cell having one MO8T connected thereto.

The sense amplifier PA is a cross-coupled MO8TQA,Q
n, and an MO8T Qo for connecting the sources of these MO8T QA and QB to the ground. Similarly,
The sense amplifier PA is a cross-coupled MO8T QA
, QB, and the source of these MO8TQA, QB,
This is MO8TQo for connecting to ground. M.O.
8TQo, Q.

When the pulse φゎ applied to the gate of becomes high level,
Sense amplifiers PA and PA become active.

The drain of MO8TQA in the sense amplifier PA is M
The data line D is connected via OS T Qo+ and Qo, respectively.
o, connected to D1, MO8T in the sense amplifier PA
The drain of Q is MO8'l' Q, o2. Q.2
data lines through each. ,D,.

Similarly, the drain of MO8TQA of sense amplifier PA is connected to the data line through MOST Qo+ and Qo, respectively. , D, and the drain of MO8TQB is connected to MO8T Qo2. Data lines are connected through Q1□ respectively. , Dl.

The drains of MO8TQA and QB are further connected to M
Common data lines CD, C via O8T QD, QD
Connected to D.

In this memory device, a patented recell array characterized by a pair of sense amplifiers and two pairs of data lines is arranged in parallel in the vertical direction of the figure, but for the sake of simplicity, this memory cell array is Not shown. Note that the memory cells in these memory cell arrays are also connected to the word line W like the illustrated memory cells. , Wo, Hit...Dummy word IDW.

Connected to DW.

Before reading memory cells, common data lines CD, C
D. Data line. , one angle I Dl l Di and M.O.
8T QA, QB, OK, M connected to the drain of the calendar
The O8T QP precharges these data lines and the drain of the MO8T to the power supply voltage V in response to a high level P Ij charge signal applied to its gate. At this time, the dummy cell DC receives this precharge signal CE via the line 30 and is set to the initial state. During this precharge period, the signal φ9 is
The sense amplifier PA is held at a low level.

FA is in an inactive state. Similarly, driver 1°A, I
The OB decoder 2o is configured to maintain its output at a low level during this precharge.

In this memory device, there are 15 address signals a. −
a14 and an address signal a complementary thereto. -a14 is used.

After the precharge period ends, driver IOA outputs address signal a. When the address signal i is at a high level, a high level voltage is output to the line 32, and when the address signal i is at a high level,
A high level voltage is output on line 34.

On the other hand, after the end of the precharge period, the decoder 20 also receives the address signals a1 to a9. When a, ~a, has a predetermined value, a high level voltage is output and the MO8T QD
, turn on the QD.

After the precharge period ends, the driver IOB connects one of the word lines W., W., . Outputs a high level voltage to one side of the

The driver JOB selects the dummy word line DW so that the memory cell connected to one data line of each data line pair and the dummy cell DC connected to the other data line are selected.
, DW selectively outputs a high level voltage.

The memory cell to be selected now is the data line. and word line W. Assume that the memory cell MC is located at the intersection with . The driver IOB outputs the word line W in response to the address signal.

Then, a high voltage is selectively output to the dummy word line DW.

As a result, the word line W along with this memory cell. All other K-connected memory cells are also read. Therefore,
Data line. and Dl and word line W. 2 at the intersection of
One memory cell MC is read and the data line is read. .

The voltage on Dl changes depending on the signal stored in the read memory cell MC.0 Similarly, two dummy cells DC at the intersection of the data line are read out. ,D
, is set as the reference voltage. In this memory device, the even-numbered data lines from the top. Ori. To read the memory cell Me connected to the address signal a. , ao are held at high level and low level, respectively, and in order to read the memory cell MC connected to the odd-numbered data line DI or Dl from the top, the address signal a. , ao are held at a low level and a high level, respectively.

Therefore, the memory cell to be selected is the word line W.

and data line. If the memory cell MC is located at the intersection of the lines 32 and 34, the driver IOA outputs a high voltage and a low voltage to the lines 32 and 34, respectively.

In this way, after the precharge period ends, the word line (
The voltages on lines 32 and 34 (including the dummy word line) are determined. At the same time, the pulse φ is changed from a low level to a high level, and the preamplifiers PA and PA are activated.

MO8T Q when the voltages on lines 32 and 34 are high and low, respectively. ,,Qo2゜Q1□,Q
1□ is on, MOST Qo+, QO
2.

Qll + Q, 2 is turned off. Therefore, the data line.

and Do are Q respectively to the sense amplifier PA provided on the right side of them. 1+Qg2, and the voltages of these data lines are amplified differentially, with one being held at a value close to the original precharge level, and the other being discharged to ground level. Data line. Ori. When the upper memory cell is selected, the decoder 20 outputs address signals a1-a,.

Since a high voltage is output in response to a1 to a9, M
O8T QD, QD are in the on state. Therefore, the drains of the MO8Ts QA and QB of the sense amplifier PA are connected to the common data lines CD and CD, respectively. Therefore,
Common data lines CD and CD are connected to data lines D0. The voltage is changed to be the same as the voltage of Do. In this way, the voltages of the common data lines CD and CD are read from the memory cell MC.
The value corresponds to the stored signal.

On the other hand, f-1faD, ,D, are each MO8T
They are connected to the sense amplifier PA on the left side of them via Qo+Q12, and the voltages of these data lines are differentially amplified, with one changing to a high level and the other changing to a low level.

Word line W. The storage signals of other memory cells located at the intersections of the data lines and other data lines (not shown) are read out in the same way, and similarly amplified by sense amplifiers (not shown).

The memory cell to be read is the word line W. and data line D1
If the memory cell MC at the intersection of
．． 34 are respectively supplied with low level and high level voltages by the driver IOA.

Therefore, MOS T Qo+ , QO2, Q1+ , Q
10 is turned on, MOS T Qo+, QO2
, "=o, Q10 is turned off. As a result, the voltage on the data line D1 is differentially amplified by the sense amplifier PA, and the voltage on the data lines D1 and Dl is
The differential width is amplified by The output of sense amplifier PA is similarly supplied to common data, IcD, and CD. In this way, the word line W. is selectively brought to a high voltage,
Even when a plurality of memory cells MC connected thereto are read, the storage signals of those memory cells are amplified by the sense amplifier PA or PA, respectively. Therefore, these memory cells MC store this amplified voltage again.
That is, it can be rewritten. Therefore, even if the reading of the memory cell is destructive reading as in the conventional one-transistor memory cell, the original storage signal can be written into each of the plurality of read memory cells.

After reading the memory cell, all signals are returned to their original levels.

In addition, the data line. , D□ * When DI or a memory cell other than the memory cell connected to DI is selected, the decoder 20 outputs a low level voltage and MO8T
0 that turns off QD and QD. Therefore, the sense amplifier PA
The output of is the common data line CD.

Not supplied to CD.

As described above, by providing sense amplifiers on the left and right sides of the two data line pairs and switching the connection between each data line pair and the sense amplifier, reading of the memory cell to be read connected to the selected word line is performed. At the same time, other memory cells connected to this word line can also be read and rewritten.

To externally store a signal in a desired memory cell, after performing the above read operation for that memory cell,
Before returning all signals to precharge levels,
The voltage of the common data lines CD, CD is set to high or low level depending on the signal to be written. After the write operation is completed, all signals are returned to their original precharge levels.

Using this memory device, the sense amplifier PA.

Since the PAs are placed on the left and right sides of the four data lines, the space equivalent to four data lines can be used as the amplifier space.

In addition, since the PA is used as an amplifier only for reading data and the PA is used as an amplifier only for rewriting, the PA does not need to drive the data line at high speed and can complete the expansion by the timing of rewriting, so the capacity can be reduced. can be made smaller, further reducing space. Accordingly, the area occupied by the PA can be increased.

Furthermore, since the read amplifiers are gathered on one side, it is not necessary to provide the common data 1lilcD and CD on both sides of the data line, but only on one side, thereby reducing space.

However, in this memory device, the transistor Q. 1゜Q,
2 and QOI * QO2 and Q. 3 + QO4 and Q(
Data line because 1B + QO4 are not turned on at the same time. l DQ I Two precharging transistors QP must be provided for Dl and Dl, respectively. If two transistors Q are provided for one data line, Q will increase significantly and the chip area required for this will increase.

[Purpose of the invention]

An object of the present invention is to reduce the number of precharge transistors Q.

[Summary of the invention]

To achieve this objective, the present invention makes the data line and the two sense amplifiers conductive during the precharge period, and precharges them using a common precharge circuit.

[Embodiments of the invention]

In this example, we will use MO8T for precharging in Fig. 1.
Of Q, MO8T QP connected to each data line and sense amplifier PA is omitted. For this purpose,
Driver IOA connects lines 32 . to 32 during the precharge period.
34, and after the precharge period ends, the address signal a is output. , aoO high and low, respectively, are output to lines 32 and 34.

When such a driver IOA is used, M 08 T Qg+ , Q, o+ during the precharge period.

Q, 021 QO21Qll I Q,, I Q10
1 Q,, 2 are turned on, so the sense amplifier PA
MO8T Q, connected to each data line. , Do
,D.

D, and MO8TQA of sense amplifier PA.

The drain of QB can also be precharged. [Effects of the Invention] According to the present invention, the number of precharge circuits can be reduced by connecting two data line pairs to two sense amplifiers. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment. PA, FA...
・Sense amplifier, MC...memory cell, DC...dummy cell. Generation? 11 da

Claims (1)

[Claims] l A pair of first. a second data line, and a pair of third data lines. a fourth data line; the second data line or the third data line. a plurality of word lines provided to intersect with a fourth data line; a plurality of memory cells provided at the intersections of the two data line pairs and the plurality of word lines; and the two data line pairs. The first signal for amplifying the signals of .
When reading a signal from one of the two data line pairs, the second sense amplifier connects the read data line pair to the first sense amplifier, and connects the other data line pair to the second sense amplifier. a switch means for connecting the first sense amplifier to the first sense amplifier; a means for outputting the amplified output of the first sense amplifier as a memory cell read signal; and a means for precharging the two data line pairs with a precharge signal. . The memory device, wherein the switch means includes means for connecting both of the two data line pairs to an eleventh second sense amplifier during the precharging.