JPS59228417A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To eliminate the effect of leakage current on an AD converting gain by driving a switch connected to an integration circuit among switches being components of a switched capacitor circuit in an identical prescribed period. CONSTITUTION:A switch Sr2 of a reference charge injection circuit 12 repeats turning on/off at all times in synchronizing with the operation of a switch Si2 and only a switch Sr1 is turned in synchronizing with an output of a comparator circuit 14. Thus, since the leakage current does not give any effect on the gain, the gain is not largely susceptible to the effect of conditions such as ambient temperature and manufacture process.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an A-D converter, and particularly to an A-D converter that is highly accurate and
S I (Lage 5c31e Integrat
ion).

[Background of the invention]

FIG. 1 is a circuit block diagram of an A-D converter previously proposed by the applicant of the present invention. In FIG. 1, 11 is a voltage input circuit, which includes a buffer amplifier 21 and switches Su and Sst.
and a switched capacitor circuit 22 consisting of a capacitor CI. Reference numeral 12 denotes a reference charge injection circuit, which is composed of a buffer amplifier 23 and a switched capacitor circuit 24 consisting of a switch Srt I Sr2 and a capacitor C2. 13 is an integration circuit, 14 is a comparison circuit, 15 is a switch control circuit, 16 is a timing control circuit, and 17 is a digital processing circuit.

FIG. 2 is a time chart showing the operation of FIG. 1, and FIGS. 2(a) and 2(b) show the switches S11. of the switched capacitor circuit 22 driven by the timing control circuit 16. Indicates the operation of SL2, a high level indicates the on state of the switch, and when the switch 8+t is on, the capacitor CI
The charge qI = CI ・Vt(C
t is the capacitance value of the capacitor CI), and the switch 81
2 is on, the charge is transferred to the integrating circuit 13.

After repeating such operations, when the output voltage of the integrating circuit 13 exceeds the threshold value of the comparing circuit 14, the output of the comparing circuit 14 is inverted. The operation of the comparator circuit 14 is shown in FIG. 2(C). Due to the inversion of the output voltage of the comparison circuit 14, the switch control circuit 15 controls the switch 8rl HSe2 of the switched capacitor circuit 24 of the reference charge injection circuit 12.
Drive once. The operation of switches St1 and 8t2 is
) and (e). That is, the reference charge injection circuit 1
The second switched capacitor circuit 24 operates in synchronization with the output of the comparison circuit 14. Due to the operation of the reference charge injection circuit 12, the reference charge qr=vt' cr
<vr is the reference voltage, C1 is the capacitance value of the capacitor CF) is transferred to the integrating circuit 13 every time. Therefore, if the polarity of the reference charge qr is reversed to the polarity of the input charge ql, the operation of the reference charge injection circuit 12 will maintain the balance of the charges in the integration circuit 13, and the output voltage will return to its original value. Therefore, the output voltage of the comparator circuit 14 also returns to its original state. Now, if the driving frequency of the switched capacitor circuit 22 of the voltage input circuit 11 is f, and the A/D conversion time is T1, and the number of operations of the switched capacitor circuit 24 of the reference charge injection circuit 12 during this period is N, then the charge of the integrating circuit 13 is According to the equilibrium condition, the following equation holds true.

ql"s・TV薯・CI"L・T=V,・C2・Nmiq,・N・・・・・・・・・・・・(1) Therefore, as a result, the operation of the reference charge injection circuit 12 The number of times N is proportional to the input voltage V+, and the number of operations N is a value obtained by digitally converting the input voltage V+.

However, according to the configuration shown in FIG. 1, it is possible to realize the switched capacitor circuit 22 with an on-chip LSI, but since the circuit as a whole becomes a high impedance circuit, it is difficult to achieve even higher precision. , this results in the disadvantage that errors due to leakage current cannot be ignored.

Next, this problem will be explained in detail. As shown in FIG. 1, the first leakage current is the leakage current Iz11@Itrl generated on the integration circuit 13 side of the swing circuit 13 connected to the integration circuit 13. Izrl is connected to switch 8I2. Se2
The signal always flows into the integrating circuit 13 regardless of the operation of the circuit.

The second leakage current is a leakage current ItI! generated on the side opposite to the integrating circuit 13 of the switches SH and Srs. *Izrx
It is. This leakage current I t1! , I tws flow into the integrating circuit 13 only when each switch is turned on. Considering these leakage currents, the charge balance condition is as follows.

(3) Formula Yoshi, -XZA1) ・・・・・・
(4) However, switch S11. SI! It is assumed that the duty of each switch is 50, and the on time of the switch 82118tjJ is the same as that of each switch So+Stx. That is, (
Equation 4) means that the leakage current Itrl causes a gain error, and other leakage currents cause an offset error. Furthermore, the leakage current has large variations due to the LSI manufacturing process or manufacturing process.
It is one of the difficult elements to manage, and has properties that vary greatly depending on temperature.It is not the cause of temperature drift in A-D conversion characteristics.High precision and high impedance This impedes power saving through

[Purpose of the invention]

The first object of the present invention is to provide an A-D circuit that does not generate gain errors due to leakage current even when using a high impedance circuit.
The purpose is to provide a converter. A second object is to provide an A-D converter that can reduce or eliminate offset errors due to leakage current even when using a high impedance circuit system.

[Summary of the invention]

The present invention integrates the output charges of a voltage input circuit including a switched capacitor circuit and a reference charge injection circuit in an integrating circuit, inputs the output of this integrating circuit to a comparator circuit, and uses the above-mentioned reference according to the output of this comparator circuit. We focused on the fact that when the charge injection circuit is operated to balance the charges and perform A-D conversion, operating the reference charge injection circuit in accordance with the output value causes errors due to leakage current. At least one of the switches constituting the switched capacitor circuit, including the reference charge injection circuit, is connected to the integration circuit side so that the influence of the leakage current is constant regardless of the output value. The switch is characterized in that it is configured to be driven at the same constant cycle.

[Embodiments of the invention]

The embodiment of the present invention shown in FIG. 4 and FIGS. 3 and 5 are as follows.
This will be explained in detail using figures.

First, an embodiment of the present invention will be explained with reference to FIG. Third
The figure is a time chart corresponding to Figure 2 when the control method for the A-D converter configured as shown in Figure 1 is improved according to the present invention, and (A) to (E) in Figure 3 are (a) in Figure 2
It corresponds to ~(e). In FIG. 3, the switch Sr2 of the reference charge injection circuit 12 in FIG. 1 is replaced by the switch Sr2 in FIG.
As shown in FIG.
11 is turned on in synchronization with the output of the comparator circuit 14 shown in (C) of the same figure, as shown in FIG. In this case, the charge Q+ injected into the integrating circuit 13 from the voltage input circuit 11 and the reference charge injection circuit 12 within the conversion time T is calculated by setting the switch operating conditions to be the same as the conditions for deriving equations (3) and (4). ...(5) The reference charge Q is also expressed as (5) with respect to the leakage current.
) with the same conditions as the expression. As a result of the above, when N is determined from the charge balance condition within the conversion time T, it becomes as follows. That is, the leakage current does not appear in the denominator term that affects the gain.

In short, according to this embodiment, the leakage current, which is greatly affected by conditions such as ambient temperature and manufacturing process, is reduced from A to D.
If the effect on conversion gain is eliminated, A-D conversion characteristics such as distortion, gain variation, and gain drift can be significantly improved (9).

FIG. 4 is a circuit diagram showing another embodiment of the present invention, in which the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted here.

FIG. 5 is a time chart of the operation shown in FIG. In FIG. 4, a switch 831 is provided before the voltage input circuit 11.
+8J! Additionally, a bias charge injection circuit 18 for injecting a constant bias charge into the integrating circuit 13 is provided. The charge injection circuit 18 includes a buffer amplifier 25
and a switched capacitor circuit 26, and the switched capacitor circuit 26 includes a switch Sb1.8bz and a capacitor C1.

Next, the operation of the above circuit configuration will be explained.

First, when converting the input voltage Vi from A to D, switch 8
Turn on N, turn off sJ*, and input the input voltage vI.

5(a) and 5(b) respectively show the switch 811 of the switched capacitor circuit 22 of the voltage input circuit 11. S
The operation of ix is exactly the same as that shown in FIG. 5(a) and (b) also show the operation of the switches 8bl and Sb2 of the switched capacitor (10) circuit 26 of the bias charge injection circuit 18, respectively, and the operation of the bias charge injection circuit 18 is as follows: The operation is the same as that of the voltage input circuit 11. Therefore, assuming that the charges Q, , Q, respectively injected from both circuits into the integrating circuit 13 within the conversion time T are the same as the conditions for deriving equations (3) and (4), the following equations are obtained. As a result, as in the case of FIG.
The output of the integrating circuit 13 is inverted when the output voltage of the integrating circuit 13 exceeds the threshold value. The operation of the comparison circuit 14 is shown in FIG. 5(C). Depending on the output voltage of the comparison circuit 14, the switch control circuit 15 controls the operation of the switch 5vIH8rt of the switched capacitor circuit 24 of the reference charge injection circuit 12. The operation of this switch 5y118rz is shown in Figure 5), (
Shown in e). That is, the reference voltage V to the capacitor C1,
Switch Sr that prevents you from charging! As in the case of FIG. 3, the ratio (11) is operated in response to the output of the comparison circuit 14. However, the switch 8rz connected to the integrating circuit 13 side in order to inject charge into the integrating circuit 13 is operated at a constant cycle in synchronization with the switches SI2.81+2. As a result, the leakage current IA,2 flowing into the integrating circuit 13 is:
The charge Q injected from the reference charge injection circuit 12 to the integration circuit 13 within time T is unrelated to the operation of the comparison circuit 14.
, ' are expressed by the following equation. However, switch 8yl
s The operating conditions for Sr2 are the same as in the case of FIG.

As a result of the above, from the charge balance condition within time T, the number of operations NI
When calculating, Q+ + Q-= Q-・・・・・・αυ・・・・・・
(12) of a. Similarly, switch SN is turned off, and switch S
j! is turned on, zero voltage is input to the voltage input circuit 11, and A-D conversion is performed for a period of time T. The number of operations N0 of switch 8+4, which is the bias output, can be calculated by setting V I = O in the a formula. obtained, becomes. Therefore, the A-D conversion output value Newt is proportional to the input voltage.
is obtained. Note that the switch S J 1 #812 is controlled by the timing control circuit 16, and (14
) is performed by the digital processing circuit 17.

As described above, according to the embodiments of the present invention described above,
Since the influence of the leakage current on the output count value is converted into an offset, the influence on the gain error can be eliminated as in the first embodiment described above (13). In equation (7), when VI=O, the risk that the output value N becomes negative due to leakage current can be eliminated by injecting bias charges. Furthermore, offset errors can also be eliminated by separately counting the offset output when vI=0 and performing offset correction as in equation (14). Also, as a result, the error due to leakage current is converted into an offset error, so by performing offset correction! Therefore, as shown in equation (14), both the gain error and offset error are not affected by leakage current, and
It is possible to obtain an A-D converter that has good stability and can easily be made highly accurate.

Note that the switched capacitor circuit may have a configuration different from that described above, and the same effect can be obtained. Furthermore, it goes without saying that the offset correction means may be implemented using other methods, such as analog means.

〔Effect of the invention〕

As discussed above, according to the present invention, gain errors due to leakage current can be prevented even when using a high impedance (14) impedance circuit, and high precision can be easily achieved.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram showing the configuration of the A-D converter proposed earlier, Fig. 2 is a time chart showing the conventional operation of Fig. 1, and Fig. 3 is the present invention in the configuration of Fig. 1. FIG. 4 is a time chart of the operation of one embodiment of the present invention.
A circuit block diagram showing another embodiment of the D converter, and FIG. 5 is a time chart showing the operation of FIG. 4. DESCRIPTION OF SYMBOLS 11... Voltage input circuit, 12... Reference charge injection circuit, 13... Integrating circuit, 14... Comparison circuit, 15...
- Switch control circuit, 16... timing control circuit,
17... Digital processing circuit, 18... Bias charge injection circuit, 21, 23.24... Buffer amplifier,
22゜24.26...Switched capacitor circuit, S
It+812 g 8rtl Srz I
Sb 11 Sbz + 811 +
812 Self-switch, CI + Cr @
Cb... Capacitor. Agent Patent Attorney Akio Takahashi (15) No./E (E) 1,400m (M)

Claims (1)

[Claims] 1. A voltage input circuit having a switched capacitor circuit, an integrating circuit that integrates the output charge of the voltage input circuit, and a reference charge having a switched capacitor circuit connected to the input of the integrating circuit. an injection circuit, a comparison circuit that receives the output of the integration circuit as an input, a switch control circuit that controls the reference charge injection circuit according to the output of the comparison circuit, a digital processing circuit, and controls the overall operation timing. and a timing control circuit, wherein at least the switches connected to the integrating circuit side among the switches configuring each of the switched capacitor circuits are configured to be driven at the same constant cycle. converter. 2. A bias charge injection circuit having a switched capacitor circuit is also connected to the input of the integrating circuit, and at least one of the switches constituting the switched capacitor circuit of the bias charge injection circuit is connected to the integrating circuit side. 2. The A/D converter according to claim 1, wherein said voltage input circuit and reference charge injection circuit have a switched capacitor circuit driven at the same constant cycle as a switch on said integration circuit side.