JPS59226943A - Shift arithmetic circuit - Google Patents

Abstract

PURPOSE:To obtain a shift arithmetic circuit having a reduced hardware quantity by securing the common use among those parts possible for common use of both left and right shift circuits. CONSTITUTION:A selection circuit 3 serves as a selector of a double input circuit of the 8-bit constitution. The output data 41 and 51 of shift circuits 4 and 5 are supplied to an input circuit of one side; while the output data 51 and 61 of shift circuits 5 and 6 are supplied to the other input circuit. These data of both input circuits are selected alternatively by 0 or 1 of the left/right selection signal land then delivered in the form of a shift result data 31. That is, the result of output data of the circuit 3 is e0e1e2f0f1f2f3f4 when the signal l is set at 0; while the data result is f0f1f2f3f4g0g1g2 when the signal l is set at 1. In this case, the output of the circuit 4 is e0, e1 and e2; while the output of the circuit 5 is f0, f1, f2, f3 and f4 respectively. Then these data are supplied to the circuit 3 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a shift arithmetic circuit used in an arithmetic circuit of a data processing device.

Prior Art As shown in FIG. 1, a conventional shift calculation circuit is composed of a right shift circuit 1, a left shift circuit 2, and a selection circuit 3 that selectively outputs the outputs of the shift circuits 1 and 2. has been done. For example, 8-bit input data a. -a7 to 0~
Taking a circuit that shifts 3 bits as an example, the left,
The right shift circuits 1 and 2 are both 8-bit four-man selectors, and the selection circuit 3 is an 8-bit two-man selector. The right shift circuit 1 receives 8-bit input data a0~&7 and 3-bit first insertion data C6~
C3 is input, and each of the four input circuits with an 8-bit configuration receives ao-a? "+" Qtt ao~a
6′.

C11e'l, aQ~a5"t" Cot et
t Qtt FLo~&4"i)" is input. The data of these four input circuits are selectively output by a selection signal applied from the outside. Left shift circuit 2
Similarly, 8-bit input data a(, "-tag and second insertion data d, -d.

is input, and according to the selection signal j) ”&Q% a7
”.

al-a7. do”,’a2~ays dot
al" j or' tLB~all dot a
tl a, 19 is selectively output. FIG. 2(a) shows the 8-bit input data "ao% a".
7'', the figure (b) shows the relationship between the number of shift bits and the output data (8 bits) when shifting to the right, and the figure (c)
) indicates the relationship between the number of shift bits during left shift and output data (8 bits).

The circuit described above consists of two 8-bit 4-person selectors and 8
One bit two-man selector is required. That is, there is a drawback that the amount of hardware increases because left and right shift circuits are required separately.

OBJECTS OF THE INVENTION An object of the present invention is to provide a shift calculation circuit which solves the above-mentioned conventional drawbacks and reduces the amount of noise by making parts that can be shared in the left and right shift circuits common. The shift arithmetic circuit of the present invention converts n-bit input data to 0.
~ In a shift calculation circuit that shifts m bits and outputs the data, the upper m bits of n bits of input data and m bits of first insertion data given from the outside are input, and the shift operation circuit shifts the m bits and outputs the shifted data. a first shift circuit dedicated to right shift that performs a right shift operation and outputs m-bit output data; and a first shift circuit dedicated to right shift that inputs the n-bit input data and performs a shift operation according to the shift selection signal to output n - m bits of output data. a second shift circuit that outputs the lower m bits of the n-bit input data and m input from the outside;
a third shift circuit dedicated to left shift which inputs bit insertion data and performs a left shift operation according to the shift selection signal to output m bits of output data; a selection circuit that selectively outputs either the output data of the first and second shift circuits or the output data of the second and third shift circuits according to a left/right selection signal inputted and given from the outside; It is characterized by having the following.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

That is, n-bit input data is input from the input data line 71 to the first to third shift circuits 4 to 6, and m-bit first insertion data 72 and m-bit second insertion data 73 are input to the first to third shift circuits 4 to 6, respectively. and is input to the third shift circuits 4 and 6.

The first insertion data is data given from the outside when shifting to the right, and the second insertion data is data given from the outside when shifting to the left. The first shift circuit 4 is a shift circuit dedicated to right shifting, receives the m-bit first inserted data and the upper m bits of the n-bit input data, and performs a shift operation by a shift selection signal 74 to shift the m-bits. Output data 41 is output. For example, in the case where 8-bit input data is shifted by .theta..about.3 bits, the first shift circuit 4 is constituted by a 4-input circuit selector having a 3-bit configuration. Now the 8-bit input data is 89%jL7”
Let the first insertion data be n C, , c2 n,
If the second insertion data is do-d, ``, then each K of the four input circuits of the first shift circuit 4 is ``a(
, al a2”, “C7aoal”2 c1 cl
ao″ν″Co cl a@ ” is input. Then, the shift selection signal 1'00″, '01', ″, ″1
The above four data are selectively output in correspondence with 1" and 0.

The 3-bit output data of the first shift circuit 4 is
e2', the shift selection signal and the first shift circuit 4
The relationship between the output data and the output data is K as shown in FIG. 4(a).

The second shift circuit 5 inputs n-bit input data 71 and outputs nm-bit output data in response to a shift selection signal 74. For example, in the above example where 8-bit input data is shifted by 0 to 3 bits, the second shift circuit 5
consists of a 4-person circuit selector with a 5-bit configuration.

Each of the four input circuits has 'a3 to a7', 'a
, ~a6 pt, ff a1~a,'.

aO-&4'' is input and selectively outputted by the shift selection signal 74. The output data of the second shift circuit 5 is ``1. □ The correspondence relationship between f4N and the shift selection signal 74 is as shown in FIG. 4(a). The third shift circuit 6 dedicated to left shift is a selector with a 3-bit configuration and 4 input circuits, which inputs the lower 3 bits "a, ~a7'" of the input data and the second insertion data "d0~a2N" and outputs a shift selection signal. 74 outputs 3-bit output data {g0~g!n.
2", a7 d, d4", "a6 a7
d(,”.

a, to a,' are input. The correspondence relationship between the output data "go" and "gt" of the third shift circuit 6 and the shift selection signal is as shown in FIG. 4(a).

The m-bit (3-bit) output data 41 output from the first shift circuit 4 and the nm output data 41 output from the second shift circuit 5
The output data 51 of bit 7 (5 bits) and the output data 61 of m bits (3 bits) output from the third shift circuit 6 are input to the selection circuit 3.

The selection circuit 3 has an 8-bit configuration (generally n bits).
The output data 41 of the first shift circuit 4 and the output data 51 of the second shift circuit 5 are input to one input circuit, and the second shift circuit 5 is input to the other input circuit. Output data 51 of the circuit 5 and output data 61 of the third shift circuit 6 are input. The data of the above both input circuits is the left and right selection signal l (l On or “1”)
A constant selection is made by X and output as shift result data 31. When the left/right selection signal l is 60'', the shift result data output from the selection circuit 3 is 'e (Ie).

e2 f,) fl f21B f4 ``Ashi, l is 71'' (7) (!: Ki tD Shift result data is''
fo flft f3 f4 go gt g2'' (see Figure 4(c)) 0 Therefore, for example, when the shift selection signal is 'oo' and the shift is to the right, the shift result data is ao-a7''.The number of shift bits output is 0. However, in the case of left shift, the shift result data is a3 to ay, dOdl d,'', and the number of shift bits is 3. The relationship between the shift selection signal and the number of shift bits during left and right shifts is as shown in FIG. 4(b)K. That is, a shift operation of 0 to 3 bits is possible.

When shifting WKn focus input data by 0 to m bits, the first and third shift circuits 4゜6 are each configured with a selector of (m+1) input circuits with m bit configuration, and the second shift circuit 5 is The selection circuit 3 may be configured with a selector of (m+1) input circuits with a (nm) bit configuration, and the selection circuit 3 may be configured with a two-person circuit selector with an n-bit configuration.

Effects of the Invention As described above, in the present invention, the second shift circuit commonly performs the shift operation of the common portion that is output even when shifting the left and right layers. Since the required number of bits of the circuit and the third shift circuit dedicated to left shift are set to the minimum necessary, there is an effect that the hardware requirement can be reduced as a whole.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional shift calculation circuit, FIG. 2 is a diagram showing data of each part of the conventional example, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. ),
(b)? (e) are the first to
FIG. 7 is a diagram showing the relationship between the output data of the third shift circuit and the shift selection signal, the relationship between the shift selection signal and the number of shift bits, and the relationship between the left/right selection signal and shift result data. In the figure, 1... right shift circuit, 2... left shift circuit, 3... selection circuit, 4... first shift circuit,
5... Second shift circuit, 6... Third shift circuit. Agent Patent Attorney Toshimune Sumita Figure 1 Figure 2 (a) (C)

Claims (1)

[Claims] In a shift operation circuit that shifts n-bit input data by O-m bits and outputs the result, the upper m bits of the n-bit input data and m-bit first insertion data given from the outside are inputted. a first shift circuit exclusively for right shifting which performs a right shift operation in response to a shift selection signal given to the output data and outputs m bits of output data; - A second shift circuit that outputs m-bit output data, inputs the lower m bits of the input data of the n pits and m-bit insertion data given from the outside, and performs a left shift operation according to the shift selection signal. a third shift circuit exclusively for left shift which outputs m-bit output data; and a third shift circuit dedicated to left shift that outputs m-bit output data; A shift calculation circuit comprising: a selection circuit that selectively outputs either the output data of the circuit or the output data of the second and third shift circuits.