JPS59225430A - チヤネル処理装置 - Google Patents

チヤネル処理装置

Info

Publication number
JPS59225430A
JPS59225430A JP10110183A JP10110183A JPS59225430A JP S59225430 A JPS59225430 A JP S59225430A JP 10110183 A JP10110183 A JP 10110183A JP 10110183 A JP10110183 A JP 10110183A JP S59225430 A JPS59225430 A JP S59225430A
Authority
JP
Japan
Prior art keywords
channel
input
output
unit
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10110183A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0130170B2 (enExample
Inventor
Nobuyuki Kikuchi
菊池 伸行
Jitsuo Masuda
増田 実夫
Takao Kato
加藤 高夫
Mitsuo Morohashi
諸橋 光男
Koichi Okamoto
浩一 岡本
Yoshifumi Ojiro
雄城 嘉史
Akira Miyata
彰 宮田
Makoto Kimura
誠 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10110183A priority Critical patent/JPS59225430A/ja
Publication of JPS59225430A publication Critical patent/JPS59225430A/ja
Publication of JPH0130170B2 publication Critical patent/JPH0130170B2/ja
Granted legal-status Critical Current

Links

JP10110183A 1983-06-07 1983-06-07 チヤネル処理装置 Granted JPS59225430A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10110183A JPS59225430A (ja) 1983-06-07 1983-06-07 チヤネル処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10110183A JPS59225430A (ja) 1983-06-07 1983-06-07 チヤネル処理装置

Publications (2)

Publication Number Publication Date
JPS59225430A true JPS59225430A (ja) 1984-12-18
JPH0130170B2 JPH0130170B2 (enExample) 1989-06-16

Family

ID=14291693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10110183A Granted JPS59225430A (ja) 1983-06-07 1983-06-07 チヤネル処理装置

Country Status (1)

Country Link
JP (1) JPS59225430A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6267647A (ja) * 1985-09-19 1987-03-27 Fujitsu Ltd 主記憶制御装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54531A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Channel control system
JPS5498140A (en) * 1978-01-20 1979-08-02 Hitachi Ltd Channel control system
JPS5569835A (en) * 1978-11-21 1980-05-26 Toshiba Corp Channel control system
JPS5569836A (en) * 1978-11-21 1980-05-26 Toshiba Corp Channel control system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54531A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Channel control system
JPS5498140A (en) * 1978-01-20 1979-08-02 Hitachi Ltd Channel control system
JPS5569835A (en) * 1978-11-21 1980-05-26 Toshiba Corp Channel control system
JPS5569836A (en) * 1978-11-21 1980-05-26 Toshiba Corp Channel control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6267647A (ja) * 1985-09-19 1987-03-27 Fujitsu Ltd 主記憶制御装置

Also Published As

Publication number Publication date
JPH0130170B2 (enExample) 1989-06-16

Similar Documents

Publication Publication Date Title
US6876561B2 (en) Scratchpad memory
AU649642B2 (en) Communications interface adapter
KR100268565B1 (ko) 다중 처리 시스템에서 타스크를 큐잉하기 위한 시스템 및 방법
EP0432978B1 (en) Apparatus for conditioning priority arbitration in buffered direct memory addressing
US7363396B2 (en) Supercharge message exchanger
CN111666242B (zh) 一种基于飞腾平台lpc总线的多路通信系统
US5630059A (en) Expedited message transfer in a multi-nodal data processing system
KR910017798A (ko) 동기 링크 인터페이스 및 비동기 호스트 프로세서 인터페이스를 갖는 종합 데이터 링크 제어기
JPH06314205A (ja) 割り込み源間の優先順位確立方法及びデータ処理システム
CN115396250A (zh) 具有一致事务排序的多插槽网络接口控制器
JP2001273154A (ja) 有限状態のマシーン制御をハードウエア実行データ構造操作により置換するパーフォーマンス向上方法およびシステム
US8160863B2 (en) System and method for connecting a logic circuit simulation to a network
JPS6054063A (ja) デ−タ転送システム
US8090893B2 (en) Input output control apparatus with a plurality of ports and single protocol processing circuit
US20040190546A1 (en) Method and apparatus for controlling management agents in a computer system on a packet-switched input/output network
US6487617B1 (en) Source-destination re-timed cooperative communication bus
GB2377138A (en) Ring Bus Structure For System On Chip Integrated Circuits
US7802026B2 (en) Method and system for processing frames in storage controllers
US7089457B2 (en) Efficient I/O retry over QDIO
JPH10283304A (ja) 割り込み要求を処理する方法及びシステム
JPS59225430A (ja) チヤネル処理装置
US8054857B2 (en) Task queuing methods and systems for transmitting frame information over an I/O interface
CN101258477B (zh) 统计引擎
KR0170595B1 (ko) 고속 병렬 컴퓨터에서 크로스바 네트웍 라우터의 송신부에 대한 소프트웨어 애뮬레이션 방법
JP3260515B2 (ja) 複数ポート記憶装置のインタフェース回路