JPS59225430A - Channel processing unit - Google Patents

Abstract

PURPOSE:To use an interface in common by sharing a function to execute a channel command word entirely in an individual channel device to prevent overrun of an input/output device and absorbing the differnece or the like of a transfer protocol in the channel device. CONSTITUTION:A channel controller 11 in an input/output processing unit 1 receives an input/output instruction from a main storage device 3 through a memory control unit 4 and reads a sub-channel 31 corresponding to the input/output device to check the status. Further, a condition code is returned to a central controller 5 to open the central controller 5. If the input/output processing unit 1 conducts input/output operation, after the central controller 5 is opened, the channel bus controller 11 applies cueing to an input/output operation cue provided in itself. Further, one input/output operation is decued from this cue, the execution command of input/output operation is given to a channel device 23.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of configuring a channel processing device for controlling a plurality of channel devices.

(bl Technology background Although channel processing devices using a common control method have existed for a long time,
There was a problem in the division of work between the common control section and the individual sections corresponding to each channel device. That is, the common control unit generally executes processes that require high-speed processing, such as command chain processing, data chain processing, and page boundary processing.

Therefore, if the above processing requests are generated from multiple channel devices at the same time, the above processing may not be completed in time.

There were many cases of overruns, and it was necessary to reconsider the division of functions between the common control section and the individual sections in the channel processing device.

With the recent trend toward higher integration of logic circuits, the increase in hardware due to improved functionality of the individual sections has become less of a problem, and improvements in the functionality of the individual sections have been desired.

(C) - Prior art and problems In the common control section in the conventional channel processing device,
In order to prevent overruns in input/output devices, there is a problem in that a complicated control method must be considered, such as by configuring a common control unit into a pipeline so that processing for multiple channel devices can be performed simultaneously.

Furthermore, there is a recent trend toward diversification of transfer protocols and transfer speeds between channel devices and input/output devices, making it difficult to cope with the conventional system in which a common control unit handles these processes.

(dl Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention prevents input/output device overruns by distributing functions such that each channel command word is processed by an individual channel device. At the same time, all differences in transfer protocols are absorbed by the individual channel devices, the interface between the common control unit and the individual channel devices is made common, and the common control unit is particularly aware of the functions unique to the channel devices. The purpose is to provide a scalable method that does not require

(6) Structure and object of the invention According to the present invention, a central control device, a channel processing device for controlling a plurality of channel devices, a memory device, a memory access control and a central control device, a memory device and a channel processing device are provided. In a data processing system that includes a memory control unit that controls the interface between devices, the channel processing unit is connected to a channel path control unit that controls input/output instructions, interrupt control, etc. related to the central control unit, and a memory access control unit that controls the interface between devices. An input/output processing unit consisting of a block for performing
A block consisting of a channel unit that executes all input/output operations related to a channel command string and a block that controls memory access of the input/output processing device can be accessed from both the channel path control unit and the channel unit. Buffer storage for transmitting possible control information is provided for each channel device, and the interface between the input/output processing device and the channel unit is unified.
This is achieved by providing a method that enables ζ control, and has the advantage of simplifying the common control unit and preventing overruns in input/output devices.

(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing an input/output processing device (IO
FIG. 3 is a diagram illustrating an example of the division of functions between a channel unit (CHU) and a channel unit (CHU).

In the drawing, 1 is an input/output processing unit (IOP),
2 is the channel unit (CHU), 3 is the main memory (MS), 4 is the memory control unit (MCI)
, 5 is a central control unit (CPU), and a main memory (MS) 3 has subchannels (corresponding to input/output devices).
SCHW) 31 is provided.

The present invention is concerned with the division of functions between the input/output processing device (IOP) 1 and the channel unit (C) Iυ) 2.

In the input/output processing bag fi (IOP) 1, 11 is a channel bus controller (CPC) that performs analysis 9 of input/output commands, interrupt processing, queuing of input/output operations, channel path selection, etc. 12 is a path handler (BH), and channel path controller (CPC) 1
1. Alternatively, access control from the channel unit (CIll) 2 to the main storage device (MS) 3;
The communication area [channel transaction buffer (CTB'')) between the channel bus controller (CPC) 11 and the channel device (CHE) 23 (described later) is
I have it for Yanel W23.

The functions of the input/output processing unit (IOP) 1 described above are the channel device (CHE) 23 and the subchannel (SCH function).
This means 31 state management. More specifically, the subchannel (SCHW) 31 is provided on the main memory (MS) 3, and is connected to the input/output processing device (1).
0P) 1 is the central control unit (CPU') 5. When analyzing the received command, or each channel device (CHE)
23, the subchannel (SCHW
) In order to check 31, the subchannel (SC) is sent and received and analyzed.

For example, for input/output instructions, this input/output processing device (
IOP) 1 channel path controller (CPC)
11 reads and analyzes the subchannel (SCIIW) 31, and if an input/output operation is involved, gives an execution instruction to the channel device (CIIB) 23.

In addition, the input/output processing unit (IOP) 1 receives the completion of the input/output processing in each channel device (CIIE) 23 and the completion status report associated with the completion operation, analyzes the status, and sends the information to the central control unit ( Performs interrupt processing for CPU 5.

On the other hand, the channel unit (CHI) 2 is an input/output interface corresponding part in each channel device (CHE) 23, and is a channel path adapter (CPA) 2.
1. The path handler adapter (BHA) 22 is
These are interface adapters with a channel path controller (CPC) 11 and a bus handler (B11) 12 in an input/output processing unit (IOP) 1, respectively. The channel equipment (CHE) 23 constituting the channel unit (CHI) 2 individually performs the following input/output operations.

■Input/output processing unit (IOP) 1 path handler (
Reading of the command address word (C) from the channel transaction buffer (CTB) 121 provided in B11) and 12.

■Reading, analysis, and execution of the channel command word (cc->) using the command address word (CAM).

■Data transfer via Path Handler (BH) 12.

■I/O interface sequence control (initial selection).

■Analysis of input/output device status.

A total of processes related to the equal channel command string are executed.

In particular, block multiplex channel mode (BMC)
), each channel device (CHB
) 23 only performs input/output operations for one subchannel (SCHW) 31, and does not perform processing for multiple subchannels (SCHW) 31 at the same time.

Therefore, each channel device (CHE) 23 does not need to be aware of subchannels (SCHW) corresponding to other input/output devices connected to the same channel device (ELLE) 23; 23 contains the subchannel information currently being processed.

Next, while referring to FIG. 1, we will outline the operations of the input/output processing unit (IOP) 1 and channel unit (CIIU) 2 during input/output command processing using FIG. 2, focusing on the division of their respective functions. Let me explain.

First, a channel path controller (CPC) 11 in an input/output processing unit (IOP) 1 is connected to a main memory (
MS) 3 through the memory control unit (MCυ) 4, input/output commands (S,
10F), learns the channel device number and subchannel number (corresponding to input/output devices), and stores the main memory (MS) 3.
Subchannels (SC) corresponding to input/output devices provided in
HW) 31 and view the status of the input/output device.

In this way, the input/output processing device (IOP) 1 receives a condition code (C) corresponding to the status of the input/output device.
C) is returned to the central control unit (CPII) 5 to release the central control unit (CPU) 5.

If the input/output processing unit (IOP) 1 executes input/output operations (i.e., CC-0>, the main memory (MS
) After reading the command address word (CAM) from 3 and releasing the central control unit (CPU) 5, the channel path controller (CPC) 11 queues it in the input/output operation queue provided in the confession. At this time, the command address word (CAW) is temporarily stored in the subchannel (SCHW) 31 in the main memory (MS) 3.
will be evacuated to.

When the channel path controller (CPC) 11 dequeues one input/output operation from the input/output operation queue, the command address is stored in the channel transaction buffer (CTB) 121 corresponding to the input/output device in the path handler (BH) 12. It stores a word (CIV) and an input/output device number, and gives an instruction to the channel device (CtlE) 23 to execute the input/output operation.

In response to the above instruction, the channel device (CIIE) 23 transfers the corresponding channel transaction buffer (CTB) 12 of the path handler (BH) 12.
1, the command address word (CAW) and input/output device number are read out via the Hass Handler Adapter (BH8) 22.

Subsequently, the channel command word (CCW) is read out using the command address word (CAM) and analyzed to execute input/output interface control and data transfer control.

Channel device (CIIE) 23 receives the channel end from the input/output device when the above input/output operation is completed.

Receive the device end and channel path adapter (
It sends an input/output operation end signal (interrupt signal) to the channel path controller (CPC) 11 via the CPA) 21, and at the same time sends an input/output operation end signal (interrupt signal) to the channel path controller (CPC) 11 via the path handler adapter (B
Pass handler (BH) 1 via HA) 22
2 Channel Transaction Buffer (CTB) 1
A completion status report will be made on 21.

Then, the channel path controller (CPC>ii) looks at the channel controller (CPC) 121 of the path handler (BH) 12 and the transaction bus sofa (CTB) 121, analyzes the status of the input/output device, and executes the central control unit (CPII).
) 5 and is controlled to interrupt the central control unit (CPU) 5.

The above describes the processing of the most common input/output commands using input/output processing unit (IOP) 1 and channel unit (CIl).
ll) We have explained the example of the division of functions in 2. When executing a disconnect type command (for example, a seek command), once the channel end is received from the input/output device in the seek execution stage, the channel device (CIIB)
23 is released. When the input/output device completes the seek operation, the channel device (CIIB) 23 starts operating again when the device end is sent to the channel device (CHE) 23 to receive the next command. ,
Channel command word (CCW) reading, analysis, execution, data transfer, input/output interface control, status reporting from input/output devices, etc. are all performed by the channel device (CH
E) 23, and the transmission and reception of the subchannel (SC) corresponding to the input/output device is performed by the input/output processing device (IOP')
1.

In addition, upon receiving the channel end, the channel device (CIIB
) 23 is released, the channel device (CHE
) 23 can of course perform input/output operations for another subchannel.

To summarize the above, the input/output processing bag N (IOP) 1 analyzes input/output commands from the central controller <cpυ) 5 and handles interrupts to the central controller (CPU) 5.

It executes access to the subchannel (SCIIW) provided in the main storage device (MS) 3, access to the main storage device 3 associated with data transfer, and the like.

The channel unit (CHU) 2 executes command interpretation associated with the execution of a channel command string, input/output interface control, completion report processing from the input/output device, etc.

Then, main memory device (MS) 3 and channel device (C)
II! ), command address word (CAM), channel command word (CC
W>.

All data word exchange is done by the path handler (BH) 12
Channel Transaction Buffer (CTB) 1
21.
□By doing this, the input/output processing device (I
The interface between OP) 2 and the channel unit (CIltl) 2 becomes clear, and control of the interface becomes easy.

In addition, since the main purpose of this explanation is to explain the division of functions between the input/output processing unit (IOP) 1 and the channel unit (CHll) 2, the input/output processing unit (IOP) 1
Although there is not much mention of the division of functions between the central control unit (CPU) and the central control unit (CPU) 5,
5 itself issues a command, the subchannel (SCHW) 31
It is also possible to read out the information and check the status of the input/output device.

(g) Effects of the Invention As explained in detail above, according to the present invention, among processes related to input/output operations, execution related to channel command strings is controlled to be performed entirely by the channel device. Therefore, in addition to simplifying the control in the input/output processing device that performs common control of input/output operations, the channel device can absorb the transfer protocol, transfer rate control, etc. related to the type of input/output device, and the input/output processing This has the effect of unifying the interface between the device and the channel device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a diagram illustrating an example of division of functions between an input/output processing device and a channel unit. In the drawing, 1 is an input/output processing unit (IOP). 2 is a channel unit (CHU), 3 is a main memory (MS), and 4 is a memory control unit (MC1l).
), 5 is the central control unit (CPtl), 11
is the channel bus controller (CPC), 121 is the channel transaction buffer (CTB),
12 is the bus handler (BH). 23 is a channel device (CIIE), 31 is a subchannel (SCHW), and queue is an input/output operation queue. Leaves (Kuchikashi) 2 Continued from Figure 1 Page 0 Inventor Akira Miyata Inside Fujitsu Limited, 1015 Kamiodanaka, Nakahara-ku, Kawasaki City 0 Inventor Makoto Kimura Inside Fujitsu Limited, 1015 Kamiodanaka, Nakahara-ku, Kawasaki City

Claims (1)

[Claims] Data processing comprising a central control unit, a channel processing device that controls a plurality of channel devices, a memory device, and a memory control unit that performs memory access control, the central control device, and interface control between the memory device and the channel processing device. In the system, each channel processing device has an input/output processing device consisting of a channel bus control unit that performs input/output instructions, interrupt control, etc. related to the central control device and a block that performs memory access control. and a channel unit that individually executes all input/output operations related to the channel command string, and a channel path control unit that controls memory access of the input/output processing device. A pamphlet storage for transmitting control information that can be accessed from both the input/output processing device and the channel unit is provided for each channel device, and the ink interface between the input/output processing device and the channel unit can be centrally controlled. channel processing device.