JPS59219958A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of an alpha-ray soft-error in a memory cell without increasing the generation of a latch-up in a circuit section of CMOS constitution by sufficiently deepening the junction depth of a well region in a CMOS circuit section while forming a memory cell circuit section in a shallow well region. CONSTITUTION:An n type well region 42 for a CMOS in deep junction depth d1 is formed to a peripheral circuit section 31 in a p type semiconductor substrate 41, and an n type well region 43 for preventing a soft error in shallow junction depth d0 is formed to a memory cell circuit section 31. Source-drain (p<+> diffusion layers 47) for a transistor are shaped in an element region isolated by a field oxide film 44 in the peripheral circuit section 31 through the implantation, etc. of an impurity. On the other hand, a p<-> diffusion layer 48 for a cell transistor, which functions as source-drain for the cell transistor and combines one electrode for a memory cell capacitor, is formed to the memory cell section 30, and a first polysilicon electrode 46 as the other electrode for the cell capacitor is shaped on the p<-> diffusion layer 48 through a gate oxide film 45, etc.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor device having a CMO8 (complementary MO8) structure, which is used for example in MOS dynamic memory, MOS static memory, etc. The present invention relates to a semiconductor device.

[Technical background of the invention]

In semiconductor memories, etc., circuit malfunctions due to alpha rays emitted from trace amounts of radioactive elements contained in resin packages, etc.
This causes a so-called α-ray soft error.

That is, for example, as shown in FIG.
3V, when α rays (α in the figure) are incident, electron-hole pairs are induced in the substrate 11, and the number of electron-hole pairs induced by this α ray is It reaches its maximum just before it disappears. In the device shown in FIG. 1, a potential is induced in the p-type substrate 11 by the potential shown in FIG. Of the electron-hole pairs generated, electrons flow into the n+ diffusion layer 12 which becomes a memory cell, changing the 'tu load: fi in the diffusion layer 12, causing a malfunction of the memory.

MOS static type memory and MOS dynamic type memory are used to prevent such α-ray soft errors.

type memory (hereinafter referred to as FLSRAM, DRAM)
(abbreviated as ), a memory cell portion is formed in an impurity well as shown in FIG.

That is, a p-well region 22 is formed on an n-type substrate 21,
In this p-well region 22, there is an n-type memory cell transistor.
A diffusion layer 23 is formed, and the n-type substrate 21 is set at, for example, +5. In such a device, a potential barrier is formed between the iqi n-type substrate 21 and the p-well 41J) (↓ region 22). The generated portion is stored in the p-well region 22.
I can't get inside. Only the portion of Itf induced in the p-well region 22 is involved in soft errors, and the incidence of soft errors can be reduced.

[Problems with background technology]

By the way, with the recent improvement in the degree of integration of semi-4C linear elements, during the heat generation of the element: +'lJ and T (i source "r11
Due to the demand for voltage reduction, CM and O3 peripheral circuits are being considered for SRAMI and even DRAM.

However, when the peripheral circuit is CMO8, LmX
Vertical and horizontal parasitic transistors are formed due to the well ti"/V structure unique to CMO8, and the launch amplifier phenomenon caused by the pnpn switch of this parasitic transistor becomes a problem. This latch-up phenomenon is particularly important as the miniaturization of elements increases. As the process progresses, the current amplification factor of the parasitic transistor increases and becomes a problem, so it is necessary to increase the junction depth of the well region to a certain level (i <) to create a structure that does not easily cause latch-up. There is.

However, as mentioned above, when the well region is made deeper, the probability that α-rays with a short range disappear within the p-well region decreases, making it impossible to effectively prevent α-ray soft errors. .

[Purpose of the invention]

This invention was made in view of the above points.
It is an object of the present invention to provide a semiconductor device that can effectively prevent the occurrence of α-ray soft errors in memory cells, which often increase the occurrence of latch-up in the CMO8 circuit section.

[Summary of the invention]

That is, in the semiconductor device according to the present invention, the semiconductor substrate O
In the CA'lO3 times 1d25 section, there is a transistor whose source and drain are diffusion layers of the same conductivity type as the substrate in the well region for CΔios, which has a conductivity type opposite to that of the substrate and has a normal junction depth, and a well region for 0MO8. A transistor whose source and drain are a diffusion layer of a conductivity type opposite to that of the substrate is appropriately formed in a portion where the above C is not formed.
MO3 well well region A well region for preventing α-ray soft errors with shallow junction depth and reverse n-type conductivity to the substrate is formed, and within this well region for preventing α-ray soft errors, diffusion for cell transistors of the same conductivity type as the substrate is formed. It is made up of layers.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 5, 1 indicates the memory cell circuit section of the device value, and L indicates the peripheral circuit section of the CMO8 configuration, and these are of course formed on the same semiconductor substrate 4. First, if the peripheral circuit portion 3 of the p-type semiconductor substrate 41 has a deep junction depth di, for example, 4μ? ) L n-type CMO8
A shallow n-type soft error prevention well region 43 having a junction depth d of 2 μm, for example, is formed in the memory cell circuit portion 30. Impurities are introduced into these well regions by thermal diffusion and ion implantation, which are used in the normal CMO8 element manufacturing process. Then, it is separated by a field oxide film 44 in the peripheral circuit section 3.
In the element region, a dirt electrode 46 is formed, for example, by a first polysilicon electrode formed on the y-doped oxide llI445.
The source and drain of the transistor (p diffusion layer 47 in FIG. 5) are formed by implanting impurities using a Gf mask. Note that an insulating film such as an oxide film formed on the semiconductor substrate 41-A is omitted and not shown in the figure. That's naive, in the peripheral circuit section 31 of FIG.
Although only the p-channel inverter transistor in which the diffusion layer 47 is formed is shown, the n-channel inverter transistor in which the n+ diffusion layer is formed on the substrate 41 with a goo upper electrode sandwiched in the region other than the n-type CMO8 well region 42 is shown. is formed.

A p-diffusion layer 48 is formed in a part of the memory cell 30, which serves as the source/rain of the cell transistor and serves as the electrode of the memory cell capacitor. On the 48 is a dirt rR jJQ
A first polysilicon electrode 46, which will become the other electrode of the cell capacitor, is formed via 45 and the like. Further, a second polysilicon electrode 49 is formed on the channel of the memory cell transistor via a dirt oxide film 45, and a cell transistor which also serves as a data line is formed at a portion facing the p-diffusion node 48 via the channel. A p-type diffusion layer of 5° is formed.

In the above manner, for example, the peripheral circuit section-3 such as a power supply circuit, etc.
The junction depth of the well region 1- is made deep, and the junction depth of the well region 1- is made shallow, and each predetermined region is formed, and an interlayer insulating film, a metal wiring layer, etc. are sequentially deposited. and configure the device.

In the above embodiment, a case was described in which the device was formed using a p-type silicon substrate, but in this case, an n-type silicon substrate was used and the conductivity type of each part was reversed to that of the above embodiment, and the CM was fabricated.
The O8 well well region 42 and the soft error prevention well region 43 may be formed of a p-type well, and the memory cell transistor may be an n-channel transistor. Although the case of a circuit section has been described, any device may be used as long as it has a memory cell section and a CMO8 circuit section on the same semiconductor substrate.

〔Effect of the invention〕

Figure 6 shows the number of electron-hole pairs generated by α particles in silicon crystal (DS, Yaney et al.;
Alpha Particle Tracksin 5
ilicon andTheir Effect on
Dynamic MOS RAM Re1iabl
ity"IEEE Trans, Electron
Devices ED・26 + 1-2 (1979)
As is clear from this,
The number of electron-hole pairs generated reaches its maximum just before the α particle disappears (when the range in FIG. 6 becomes O).

Energy distribution (α-ray emission energy spectrum of gold-plated metal cap, Hitachi Review Vol. 1.64 JPN 7 (1
982-7) P23-26 (Yoshishi crush) is shown. In addition to these particles, there are also quite a large number of α particles having an energy of 31 VLeV or less, that is, a range of about 10 μnL or less.

Therefore, by reducing the depth of the soft error prevention well region in the memory cell portion, soft errors caused by alpha rays, which have a particularly short range, can be effectively prevented.

As described above, according to the present invention, since the junction depth of the well region of the CMO8 circuit section is made sufficiently deep, and the memory cell circuit section is formed in the shallow well region, latch-up in the circuit section of the 6MO8 configuration is achieved. It is possible to provide a semiconductor device that can effectively prevent the occurrence of α-ray soft errors in memory cells without increasing the occurrence of α-ray soft errors.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view explaining the principle of α-ray soft error generation, Figure 2 is a diagram showing the potential of the device in Figure 1, and Figure 3 is a diagram showing the potential of the device in Figure 1.
FIG. 4 is a diagram showing the potential of the device of FIG. 3, Section 5 is a cross-sectional diagram explaining a semiconductor device according to an embodiment of the present invention, 6th
The figure is a graph showing the number of electron-hole pairs generated by α particles in silicon crystal, Figure 7 is a graph showing the 13q relationship between the energy of α particles and the range in silicon, and Figure 8 is a graph showing the number of electron-hole pairs generated by α particles in silicon crystal. It is a graph showing the energy distribution of α particles. 3θ...Memory cell circuit, 31...Peripheral circuit section, 4
ノ...Semiconductor substrate, 42...Well region for CMOS, 43...Well region for preventing soft errors, 4
4...Field oxide film, 45...Dart oxide film,
46... First polysilicon electrode, 46G... r-upper electrode, 47... p diffusion layer, 48... p-diffusion layer for cell transistor, 49... second polysilicon electrode, 50 ...P diffusion layer for cell transistor. Takehiko Suzue, patent attorney

Claims (1)

[Claims] On the same semiconductor substrate, a CMO8 circuit section incorporating a transistor with a source/drain of a four-conductivity type is provided in a well region for OMO8 of a conductivity type opposite to that of the substrate, and a transistor is provided in a well region of a conductivity type opposite to that of the substrate. In a semiconductor device in which a memory circuit section is formed in which a cell transistor is formed with a region of the same conductivity type as the substrate, the junction depth of the well region of the memory cell circuit section is set to reduce α-ray soft errors. A semiconductor device in which the depth of the junction is shallower than the junction depth of the well for MO8.