JPS59217336A - Hybrid integrated circuit and substrate thereof - Google Patents

Hybrid integrated circuit and substrate thereof

Info

Publication number
JPS59217336A
JPS59217336A JP58091672A JP9167283A JPS59217336A JP S59217336 A JPS59217336 A JP S59217336A JP 58091672 A JP58091672 A JP 58091672A JP 9167283 A JP9167283 A JP 9167283A JP S59217336 A JPS59217336 A JP S59217336A
Authority
JP
Japan
Prior art keywords
circuit
aluminum
wire
paste
aluminum foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58091672A
Other languages
Japanese (ja)
Other versions
JPH025311B2 (en
Inventor
Kazuo Kato
和男 加藤
Tatsuo Nakano
辰夫 中野
Shinichiro Asai
新一郎 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP58091672A priority Critical patent/JPS59217336A/en
Publication of JPS59217336A publication Critical patent/JPS59217336A/en
Publication of JPH025311B2 publication Critical patent/JPH025311B2/ja
Granted legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To make connection between a circuit and a semiconductor, chip condenser, chip resistor, etc. easy by forming an aluminum circuit and partially forming a metal paste circuit which can be soldered to the aluminum circuit. CONSTITUTION:An insulation layer 2 is stacked on a metal substrate 1, a circuit 3 consisting of aluminum foil is formed on it and a circuit 4 consisting of copper paste which can be soldered and silver paste 4' are partially formed on the circuit 3. A heat sink 6 and an external lead terminal 8 are connected with solder 5 to the copper paste circuit 4. A transistor 9 for high power is connected to the circuit 3 by a thick aluminum wire 7. A transistor 9' for small signal is also connected to the circuit 3 by a thin aluminum wire 7'. The transistor 9' for small signal is fixed on the circuit 3 with silver paste 4'. The circuit consisting of aluminum foil has high bonding strength with wider bonding conditions. It also has superior wire bonding capability using a gold wire.

Description

【発明の詳細な説明】 本発明は、絶縁物層にアルミニウム回路やアルミニウム
回路に金属ペースト回路を部分的に形成し、アルミニウ
ム線や金線による半導体等と回路との結ｍが容易に行え
、更に半田付による部品接続をも可能とした混成集積回
路及び基板に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention partially forms an aluminum circuit on an insulating layer or a metal paste circuit on an aluminum circuit, and easily connects a semiconductor or the like to the circuit using an aluminum wire or a gold wire. Furthermore, the present invention relates to a hybrid integrated circuit and a board that enable component connection by soldering.

従来、混成集積回路は、セラミックやガラス基板上に抵
抗体やトランジスターの如き回路部品を適宜付着したも
の、あるいはアルミニウムまたは鉄等の金属基板上に絶
縁層を設け、この北に回路を組入込む方式が一般的であ
る。Traditionally, hybrid integrated circuits have been constructed by attaching circuit components such as resistors and transistors to a ceramic or glass substrate, or by providing an insulating layer on a metal substrate such as aluminum or iron, and incorporating a circuit on the north side of this. This method is common.

これらの基板の上には、半田付による半導体のダイボン
ディング、外部リード端子の接続、チップコンデンサー
及びチップ抵抗等チップ部品の取付が行なわれる。また
半導体と回路との接続には金線又はアルミニウム線によ
るワイヤーボンディングが行なわれ、特にハイパワー用
の混成集積回路においては、２００〜５００μのアルミ
ニウム太線によるワイヤーボンディングが安価なため行
なわれている。On these boards, die bonding of semiconductors by soldering, connection of external lead terminals, and attachment of chip parts such as chip capacitors and chip resistors are performed. Wire bonding using gold wire or aluminum wire is used to connect semiconductors and circuits, and wire bonding using thick aluminum wires of 200 to 500 .mu.m is used because it is inexpensive, especially in high-power hybrid integrated circuits.

このアルミニウム線による接続においては、通常回路に
用いられる銅が酸化され易いため、貴金属メッキによる
処理、ニッケルメッキ（％公昭５２−５４６１−ｎ＞、
アルミニウムの蒸着（特開昭５ｌ−２Ｂ６６２号）及び
金属ペレットの接着（ｌｆｆ、公昭４５−３７１１０号
）、等各種の提案があった。しかしながら、メッキによ
る場合にはメッキ設備を必要とする他にメッキの表面精
度、層厚２−を吉理することが必要である。また、金属
ペレットの接着の場合は、接層個数が半導体のダイボン
ディング故より多く、これらの作業はきわめて煩雑な１
手業である。In connection with this aluminum wire, since the copper normally used in the circuit is easily oxidized, treatment with noble metal plating, nickel plating (%Koshō 52-5461-n>,
Various proposals have been made, such as vapor deposition of aluminum (Japanese Patent Application Laid-Open No. 51-2B662) and adhesion of metal pellets (LFF, Publication No. 45-37110). However, in the case of plating, in addition to requiring plating equipment, it is also necessary to ensure the surface accuracy and layer thickness of the plating. In addition, in the case of bonding metal pellets, the number of bonded layers is greater than that of semiconductor die bonding, and these operations are extremely complicated.
It is handiwork.

本発明は、かかる欠点を解決したものであり、絶縁物層
にアルミニウム回路の形成、さらにアルミニウム回路に
半田付可能な金属ペースト回路を部分的に形成すること
により、半導体、チップコンデンサー、チップ抵抗等と
回路との接続が容易となる混成集積回路及び基板を提供
するものである。The present invention solves these drawbacks, and by forming an aluminum circuit on an insulating layer and partially forming a solderable metal paste circuit on the aluminum circuit, semiconductors, chip capacitors, chip resistors, etc. The present invention provides a hybrid integrated circuit and a substrate that can be easily connected to a circuit.

すなわち本発明は、絶縁物層又は金属基板ｆ／：槓層し
た絶縁９勿層にアルミニウム箔回路と部分的に半田付可
能な金属ペースト回路とを順次積層した基板及び前記基
板の金属ペースト回路で、半田付ｊ　　　　による回路
接続を行い、又アルミ−ラム消回路で半導体のワイヤー
ボンディングによる回路接続を行ったことを特徴とする
。That is, the present invention provides a substrate in which an aluminum foil circuit and a partially solderable metal paste circuit are sequentially laminated on an insulating layer or a metal substrate f/: a layered insulating layer, and a metal paste circuit of the substrate. , the circuit connection is made by soldering, and the circuit connection is made by semiconductor wire bonding with an aluminum-ram eraser circuit.

以下図面により本発明の詳細な説明する。The present invention will be explained in detail below with reference to the drawings.

図■は、本発明による混成業績回路の一断面図を示した
ものである。基板としては、金属基板１上に絶縁物層２
を槓ノーシ、その上にアルミニウム箔から成る回路３が
形成され、半田付可能な銅ペーストによる回路４及び銀
ペースト４′がその上に部分的に形成されたものが使用
されている。図中９は、ハイパワー用のトランジスター
であり、ここから生じる熱は、鬼−トシンクロで逃がし
ている。この−一トシンクロは、図の様に半田５で銅ベ
ー７）による回路４に接続されている。また外部リード
端子８も銅ペーストによる回路４に半田５により接続さ
れている。Figure ■ shows a cross-sectional view of the hybrid performance circuit according to the present invention. As a substrate, an insulating layer 2 is formed on a metal substrate 1.
A circuit 3 made of aluminum foil is formed thereon, and a circuit 4 made of solderable copper paste and a silver paste 4' are partially formed thereon. Reference numeral 9 in the figure is a high power transistor, and the heat generated from this is dissipated by synchronization. This -1 synchronizer is connected to a circuit 4 formed by a copper base 7) with solder 5 as shown in the figure. External lead terminals 8 are also connected to the circuit 4 made of copper paste by solder 5.

一方、ハイパワー用トランジスター９は、アルミニウム
箔から成る回路３にアルミニウム太線７により接続され
ている。また小信号用トランジスター９′もアルミニウ
ム箔から成る回路３にアルミニウム細線７′により接続
されている。なお小信号用トランジスター９′は、銀ペ
ースト４′によりアルミニウム箔から成る回路３上に固
着されている。On the other hand, the high power transistor 9 is connected to the circuit 3 made of aluminum foil by a thick aluminum wire 7. The small signal transistor 9' is also connected to the circuit 3 made of aluminum foil by a thin aluminum wire 7'. Note that the small signal transistor 9' is fixed onto the circuit 3 made of aluminum foil with a silver paste 4'.

本発明に用いる基板としては、金属基板上に絶縁物層を
設け、アルミニウムｆ６から成る回路および半田付ムエ
能な金属ペーストから成る回路を設けたもの、又は、金
属基板のない絶縁物層の上にアルミニウム箔から成る回
路および該アルミニウム箔回路に半田付ＯＴ能々金属ペ
ーストから成る回路を設けたものである。The substrate used in the present invention may be one in which an insulating layer is provided on a metal substrate and a circuit made of aluminum F6 and a circuit made of a solderable metal paste, or one in which an insulating layer without a metal substrate is provided. A circuit made of aluminum foil and a circuit made of soldered OT metal paste are provided on the aluminum foil circuit.

金属基板としては、良熱伝導性の肉厚０．１〜６．０朋
のアルミニウム、鉄等が用いられ、絶縁物層としては、
無機粉体を含有する高分子樹脂絶縁層、ガラス繊維を含
有する高分子樹脂絶縁層及び耐熱性高分子樹脂絶縁層が
用いられる。前記無機粉体としては、ボロンナイトライ
ド、ベリリヤ、アルミナ、シリカ、マグネシア等が好ま
しく、高分子樹脂としては、エポキシ樹脂、フｘ　／　
−／ｌ／　樹脂、シリコン樹脂、ポリイミド樹脂等が好
ましい。As the metal substrate, aluminum, iron, etc. with a wall thickness of 0.1 to 6.0 mm with good thermal conductivity is used, and as the insulating layer,
A polymer resin insulation layer containing inorganic powder, a polymer resin insulation layer containing glass fiber, and a heat-resistant polymer resin insulation layer are used. The inorganic powder is preferably boron nitride, beryllia, alumina, silica, magnesia, etc., and the polymer resin is epoxy resin, fux/
-/l/ resin, silicone resin, polyimide resin, etc. are preferred.

またアルミニウム・泪から成る回路に用いられるアルミ
ニウム箔の厚さは、５〜１００μが好ましい。Further, the thickness of the aluminum foil used in the circuit made of aluminum is preferably 5 to 100 microns.

本発明に首う半田付可能な金属ペーストとは、銅や銀等
の半田付可能々金属の粉末をエポキシ樹脂ポリイミド樹
脂等のＭ機物に充填したペーストのことであり、例えば
アサヒ化研ＪＲ（商品名ＡＣＰ　−ン　′ ０３０２があげられ、加熱することにより、アルミ箔上
に接着し、半田付可能な回路を形成でき、通常は、スク
リーン印刷により回路形成される。The solderable metal paste applicable to the present invention refers to a paste in which powder of a solderable metal such as copper or silver is filled into a M material such as epoxy resin or polyimide resin, such as Asahi Kaken JR (The product name is ACP-N' 0302. By heating, it can be bonded onto aluminum foil to form a solderable circuit. Usually, the circuit is formed by screen printing.

次に本発明のアルミニウム箔から成る回路上に５０μの
アルミニウム線ヲ超音波ワイヤーポンディングした時の
ワイヤーボンディング条件中とボンディング強度（平均
値）の例を第１表に示した。Next, Table 1 shows examples of wire bonding conditions and bonding strengths (average values) when a 50 μm aluminum wire was ultrasonically wire bonded onto a circuit made of the aluminum foil of the present invention.

実験は、１．５ｍｍ厚のアルミニウム板に４０μのアル
ミニウム箔を、フィラー人りエポキシ樹脂で接合した金
属基板を用い、この基板のアルカリエツチングによりア
ルミニウム箔から成る回路を形成し、更にその上に銅粉
人りエポキシ樹脂系接着剤のスクリーン印刷により、半
田付可能な回路を形成した回路形成済基板を用いてワイ
ヤーボンディング試験を行った。比較のために６５μの
銅箔上に６μのニッケルメッキをした基板で同様の超音
波ワイヤーボンディング性化みたところ、第２表に示す
とうりボンディング強度は最高で３０ｇ（デンションデ
ージによる測定）であり、ボンディング条件中は第１表
よりも狭いことがわかった。The experiment used a metal substrate made by bonding a 40μ aluminum foil to a 1.5mm thick aluminum plate using filler-filled epoxy resin. This substrate was etched with alkali to form a circuit made of the aluminum foil, and then copper was added on top of it. A wire bonding test was conducted using a circuit board with a solderable circuit formed by screen printing with a powdered epoxy resin adhesive. For comparison, we performed similar ultrasonic wire bonding on a board with 6μ thick nickel plating on 65μ copper foil, and as shown in Table 2, the maximum bonding strength was 30g (as measured by Denstion Dage). It was found that the bonding conditions were narrower than those shown in Table 1.

従って本発明によるアルミニウム箔から成る回路を用い
た方がボンディング強度が高く、ボンディング条件中も
広いことがわかる。また金線によるワイヤーボンディン
グ性もテストしたところも同様に良好なことがわかった
。Therefore, it can be seen that the bonding strength is higher and the bonding conditions are wider when using the circuit made of the aluminum foil according to the present invention. We also tested wire bonding properties using gold wire and found that they were similarly good.

第１表 第２表 なお二〇内の数字は、テンションｒ−ゾによるワイヤー
ボンディング強度（ｇ）’ｒ示し、また１０回のワイヤ
ーボンディングの成功率は、○：　１００％ △：　９０〜８０優 Ｘ：　７０％以下 で表わした。The numbers in 20 in Table 1 and Table 2 indicate the wire bonding strength (g)'r due to tension r-zo, and the success rate of wire bonding after 10 times is: ○: 100% △: 90 to 80 excellent X: Expressed as 70% or less.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は、本発明の実施例の断面図である。 符号１・・・金属基板 ２・・絶縁物層 ３・・アルミニウム箔から成る回路 ４・・・半田付可能な銅ペーストから成る回路４′・・
・銀ペースト ５・・半田 ６・　ヒートシンク ７・・・アルミニウム太線 ７′・・・アルミニウム細線 Ｂ・・・外部リード端子 ９・パワートランジスター ９′・・・小信号トランジスター 特許出願人　電気化学工業株式会社The drawings are cross-sectional views of embodiments of the invention. Reference numeral 1...Metal substrate 2...Insulator layer 3...Circuit 4 made of aluminum foil...Circuit 4' made of solderable copper paste...
- Silver paste 5 - Solder 6 - Heat sink 7 - Aluminum thick wire 7' - Aluminum thin wire B - External lead terminal 9 - Power transistor 9' - Small signal transistor Patent applicant Denki Kagaku Kogyo Co., Ltd.

Claims (1)

【特許請求の範囲】 １）絶縁物層、又は金属基板を積層した絶縁物層に、ア
ルミニウム箔回路と部分的に半田付可能な金属ペースト
回路とを順次積層したことを特徴とする混成業績回路用
基板。 ２）絶縁物層、又は金属基板を積層した絶縁物層に、ア
ルミニウム箔回路と部分的に半田付可能な金属ペースト
回路とを順次積層し、前記金属ペースト回路で半田付に
よる回路接続を行い、又アルミニウム箔回路で半導体の
ワイヤーボンディングによる回路接続を行ったことを特
徴とする混成集積回路。[Claims] 1) A hybrid performance circuit characterized in that an aluminum foil circuit and a partially solderable metal paste circuit are sequentially laminated on an insulating layer or an insulating layer laminated with a metal substrate. board for. 2) sequentially stacking an aluminum foil circuit and a partially solderable metal paste circuit on an insulator layer or an insulator layer laminated with a metal substrate, and performing circuit connection by soldering with the metal paste circuit; Further, a hybrid integrated circuit is characterized in that the circuit is connected by semiconductor wire bonding using an aluminum foil circuit.
JP58091672A 1983-05-25 1983-05-25 Hybrid integrated circuit and substrate thereof Granted JPS59217336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58091672A JPS59217336A (en) 1983-05-25 1983-05-25 Hybrid integrated circuit and substrate thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58091672A JPS59217336A (en) 1983-05-25 1983-05-25 Hybrid integrated circuit and substrate thereof

Publications (2)

Publication Number Publication Date
JPS59217336A true JPS59217336A (en) 1984-12-07
JPH025311B2 JPH025311B2 (en) 1990-02-01

Family

ID=14032969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58091672A Granted JPS59217336A (en) 1983-05-25 1983-05-25 Hybrid integrated circuit and substrate thereof

Country Status (1)

Country Link
JP (1) JPS59217336A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327013A (en) * 1992-04-30 1994-07-05 Motorola, Inc. Solder bumping of integrated circuit die

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591896A (en) * 1978-12-28 1980-07-11 Fuji Electric Co Ltd Circuit board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591896A (en) * 1978-12-28 1980-07-11 Fuji Electric Co Ltd Circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327013A (en) * 1992-04-30 1994-07-05 Motorola, Inc. Solder bumping of integrated circuit die

Also Published As

Publication number Publication date
JPH025311B2 (en) 1990-02-01

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